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https://github.com/RPCS3/llvm-mirror.git
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Revert "[llvm][sve] Lowering for VLS truncating stores" because it
causes a seg fault (see https://reviews.llvm.org/D104471). This reverts commit c305557acdaad453e32309d575fe9c6c7090c099.
This commit is contained in:
Amy Huang
parent
e10d9fcec5
commit
f2ec69fb59
@ -1271,14 +1271,6 @@ public:
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getTruncStoreAction(ValVT, MemVT) == Custom);
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}
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virtual bool canCombineTruncStore(EVT ValVT, EVT MemVT,
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bool LegalOnly) const {
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if (LegalOnly)
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return isTruncStoreLegal(ValVT, MemVT);
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return isTruncStoreLegalOrCustom(ValVT, MemVT);
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}
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/// Return how the indexed load should be treated: either it is legal, needs
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/// to be promoted to a larger size, needs to be expanded to some other code
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/// sequence, or the target has a custom expander for it.
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@ -18097,11 +18097,10 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
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// If this is an FP_ROUND or TRUNC followed by a store, fold this into a
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// truncating store. We can do this even if this is already a truncstore.
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if ((Value.getOpcode() == ISD::FP_ROUND ||
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Value.getOpcode() == ISD::TRUNCATE) &&
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Value.getNode()->hasOneUse() && ST->isUnindexed() &&
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TLI.canCombineTruncStore(Value.getOperand(0).getValueType(),
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ST->getMemoryVT(), LegalOperations)) {
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if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
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&& Value.getNode()->hasOneUse() && ST->isUnindexed() &&
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TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
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ST->getMemoryVT())) {
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return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
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Ptr, ST->getMemoryVT(), ST->getMemOperand());
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}
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@ -1241,13 +1241,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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}
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}
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// SVE supports truncating stores of 64 and 128-bit vectors
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setTruncStoreAction(MVT::v2i64, MVT::v2i8, Custom);
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setTruncStoreAction(MVT::v2i64, MVT::v2i16, Custom);
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setTruncStoreAction(MVT::v2i64, MVT::v2i32, Custom);
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setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
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setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
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for (auto VT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32,
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MVT::nxv4f32, MVT::nxv2f64}) {
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setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
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@ -1494,16 +1487,6 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
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setCondCodeAction(ISD::SETUNE, VT, Expand);
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}
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// Mark integer truncating stores as having custom lowering
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if (VT.isInteger()) {
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MVT InnerVT = VT.changeVectorElementType(MVT::i8);
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while (InnerVT != VT) {
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setTruncStoreAction(VT, InnerVT, Custom);
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InnerVT = InnerVT.changeVectorElementType(
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MVT::getIntegerVT(2 * InnerVT.getScalarSizeInBits()));
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}
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}
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// Lower fixed length vector operations to scalable equivalents.
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setOperationAction(ISD::ABS, VT, Custom);
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setOperationAction(ISD::ADD, VT, Custom);
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@ -4547,7 +4530,7 @@ SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
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EVT MemVT = StoreNode->getMemoryVT();
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if (VT.isVector()) {
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if (useSVEForFixedLengthVectorVT(VT, true))
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if (useSVEForFixedLengthVectorVT(VT))
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return LowerFixedLengthVectorStoreToSVE(Op, DAG);
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unsigned AS = StoreNode->getAddressSpace();
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@ -4559,8 +4542,7 @@ SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
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return scalarizeVectorStore(StoreNode, DAG);
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}
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if (StoreNode->isTruncatingStore() && VT == MVT::v4i16 &&
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MemVT == MVT::v4i8) {
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if (StoreNode->isTruncatingStore()) {
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return LowerTruncateVectorStore(Dl, StoreNode, VT, MemVT, DAG);
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}
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// 256 bit non-temporal stores can be lowered to STNP. Do this as part of
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@ -15140,29 +15122,6 @@ static bool performTBISimplification(SDValue Addr,
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return false;
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}
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static SDValue foldTruncStoreOfExt(SelectionDAG &DAG, SDNode *N) {
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assert((N->getOpcode() == ISD::STORE || N->getOpcode() == ISD::MSTORE) &&
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"Expected STORE dag node in input!");
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if (auto Store = dyn_cast<StoreSDNode>(N)) {
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if (!Store->isTruncatingStore())
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return SDValue();
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SDValue Ext = Store->getValue();
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auto ExtOpCode = Ext.getOpcode();
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if (ExtOpCode != ISD::ZERO_EXTEND && ExtOpCode != ISD::SIGN_EXTEND &&
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ExtOpCode != ISD::ANY_EXTEND)
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return SDValue();
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SDValue Orig = Ext->getOperand(0);
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if (Store->getMemoryVT() != Orig->getValueType(0))
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return SDValue();
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return DAG.getStore(Store->getChain(), SDLoc(Store), Orig,
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Store->getBasePtr(), Store->getPointerInfo(),
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Store->getAlign());
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}
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return SDValue();
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}
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static SDValue performSTORECombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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SelectionDAG &DAG,
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@ -15174,9 +15133,6 @@ static SDValue performSTORECombine(SDNode *N,
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performTBISimplification(N->getOperand(2), DCI, DAG))
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return SDValue(N, 0);
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if (SDValue Store = foldTruncStoreOfExt(DAG, N))
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return Store;
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return SDValue();
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}
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@ -54,15 +54,6 @@ public:
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MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
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bool *IsFast = nullptr) const override;
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virtual bool canCombineTruncStore(EVT ValVT, EVT MemVT,
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bool LegalOperations) const override {
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// R600 has "custom" lowering for truncating stores despite not supporting
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// those instructions. If we allow that custom lowering in the DAG combiner
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// then all truncates are merged into truncating stores, giving worse code
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// generation. This hook prevents the DAG combiner performing that combine.
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return isTruncStoreLegal(ValVT, MemVT);
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}
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private:
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unsigned Gen;
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/// Each OpenCL kernel has nine implicit parameters that are stored in the
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@ -36,7 +36,10 @@ define void @masked_gather_v2i8(<2 x i8>* %a, <2 x i8*>* %b) #0 {
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; CHECK-NEXT: cmpne [[MASK:p[0-9]+]].s, [[PG0]]/z, z[[CMP]].s, #0
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; CHECK-NEXT: ld1sb { z[[RES:[0-9]+]].d }, [[MASK]]/z, [z[[PTRS]].d]
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; CHECK-NEXT: xtn v[[XTN:[0-9]+]].2s, v[[RES]].2d
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; CHECK-NEXT: st1b { z[[XTN]].s }, [[PG0]], [x0]
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; CHECK-NEXT: mov [[RES_HI:w[0-9]+]], v[[XTN]].s[1]
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; CHECK-NEXT: fmov [[RES_LO:w[0-9]+]], s[[XTN]]
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; CHECK-NEXT: strb [[RES_LO]], [x0]
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; CHECK-NEXT: strb [[RES_HI]], [x0, #1]
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; CHECK-NEXT: ret
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%cval = load <2 x i8>, <2 x i8>* %a
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%ptrs = load <2 x i8*>, <2 x i8*>* %b
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@ -58,7 +61,8 @@ define void @masked_gather_v4i8(<4 x i8>* %a, <4 x i8*>* %b) #0 {
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; CHECK-NEXT: ld1sb { [[RES:z[0-9]+]].d }, [[MASK]]/z, {{\[}}[[PTRS]].d]
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; CHECK-NEXT: uzp1 [[UZP1:z[0-9]+]].s, [[RES]].s, [[RES]].s
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; CHECK-NEXT: uzp1 z[[UZP2:[0-9]+]].h, [[UZP1]].h, [[UZP1]].h
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; CHECK-NEXT: st1b { z[[UZP2]].h }, [[PG0]], [x0]
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; CHECK-NEXT: uzp1 v[[UZP3:[0-9]+]].8b, v[[UZP2]].8b, v[[UZP2]].8b
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; CHECK-NEXT: str s[[UZP3]], [x0]
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; CHECK-NEXT: ret
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%cval = load <4 x i8>, <4 x i8>* %a
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%ptrs = load <4 x i8*>, <4 x i8*>* %b
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@ -174,7 +178,10 @@ define void @masked_gather_v2i16(<2 x i16>* %a, <2 x i16*>* %b) #0 {
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; CHECK-NEXT: cmpne [[MASK:p[0-9]+]].s, [[PG0]]/z, z[[CMP]].s, #0
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; CHECK-NEXT: ld1sh { z[[RES:[0-9]+]].d }, [[MASK]]/z, [z[[PTRS]].d]
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; CHECK-NEXT: xtn v[[XTN:[0-9]+]].2s, v[[RES]].2d
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; CHECK-NEXT: st1h { z[[RES]].s }, [[PG0]], [x0]
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; CHECK-NEXT: mov [[RES_HI:w[0-9]+]], v[[XTN]].s[1]
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; CHECK-NEXT: fmov [[RES_LO:w[0-9]+]], s[[XTN]]
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; CHECK-NEXT: strh [[RES_LO]], [x0]
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; CHECK-NEXT: strh [[RES_HI]], [x0, #2]
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; CHECK-NEXT: ret
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%cval = load <2 x i16>, <2 x i16>* %a
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%ptrs = load <2 x i16*>, <2 x i16*>* %b
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@ -1,218 +0,0 @@
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; RUN: llc -aarch64-sve-vector-bits-min=128 < %s | FileCheck %s -D#VBYTES=16 -check-prefix=NO_SVE
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -D#VBYTES=32 -check-prefixes=CHECK,VBITS_EQ_256
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; RUN: llc -aarch64-sve-vector-bits-min=384 < %s | FileCheck %s -D#VBYTES=32 -check-prefixes=CHECK
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=640 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=768 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=896 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1024 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_1024,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1152 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_1024,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1280 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_1024,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1408 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_1024,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1536 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_1024,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1664 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_1024,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1792 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_1024,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1920 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_GE_1024,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -D#VBYTES=256 -check-prefixes=CHECK,VBITS_GE_2048,VBITS_GE_1024,VBITS_GE_512
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target triple = "aarch64-unknown-linux-gnu"
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; Don't use SVE when its registers are no bigger than NEON.
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; NO_SVE-NOT: ptrue
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define void @store_trunc_v2i64i8(<2 x i64>* %ap, <2 x i8>* %dest) #0 {
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; CHECK-LABEL: store_trunc_v2i64i8
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; CHECK: ldr q[[Q0:[0-9]+]], [x0]
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; CHECK: ptrue p[[P0:[0-9]+]].d, vl2
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; CHECK-NEXT: st1b { z[[Q0]].d }, p[[P0]], [x{{[0-9]+}}]
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; CHECK-NEXT: ret
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%a = load <2 x i64>, <2 x i64>* %ap
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%val = trunc <2 x i64> %a to <2 x i8>
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store <2 x i8> %val, <2 x i8>* %dest
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ret void
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}
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define void @store_trunc_v4i64i8(<4 x i64>* %ap, <4 x i8>* %dest) #0 {
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; CHECK-LABEL: store_trunc_v4i64i8
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; CHECK: ptrue p[[P0:[0-9]+]].d, vl4
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; CHECK-NEXT: ld1d { [[Z0:z[0-9]+]].d }, p0/z, [x0]
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; CHECK-NEXT: st1b { z[[Q0]].d }, p[[P0]], [x{{[0-9]+}}]
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; CHECK-NEXT: ret
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%a = load <4 x i64>, <4 x i64>* %ap
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%val = trunc <4 x i64> %a to <4 x i8>
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store <4 x i8> %val, <4 x i8>* %dest
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ret void
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}
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define void @store_trunc_v8i64i8(<8 x i64>* %ap, <8 x i8>* %dest) #0 {
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; CHECK-LABEL: store_trunc_v8i64i8:
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; VBITS_GE_512: ptrue p[[P0:[0-9]+]].d, vl8
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; VBITS_GE_512-NEXT: ld1d { [[Z0:z[0-9]+]].d }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1b { [[Z0]].d }, p[[P0]], [x{{[0-9]+}}]
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; VBITS_GE_512-NEXT: ret
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; Ensure sensible type legalisation
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; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
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; VBITS_EQ_256-DAG: ld1d { [[Z0:z[0-9]+]].d }, [[PG]]/z, [x8]
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; VBITS_EQ_256-DAG: ld1d { [[Z1:z[0-9]+]].d }, [[PG]]/z, [x0]
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; VBITS_EQ_256-DAG: ptrue [[PG]].s, vl4
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; VBITS_EQ_256-DAG: uzp1 [[Z0]].s, [[Z0]].s, [[Z0]].s
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; VBITS_EQ_256-DAG: uzp1 [[Z1]].s, [[Z1]].s, [[Z1]].s
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; VBITS_EQ_256-DAG: splice [[Z1]].s, [[PG]], [[Z1]].s, [[Z0]].s
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; VBITS_EQ_256-DAG: ptrue [[PG]].s, vl8
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; VBITS_EQ_256-DAG: st1b { [[Z1]].s }, [[PG]], [x1]
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; VBITS_EQ_256-DAG: ret
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%a = load <8 x i64>, <8 x i64>* %ap
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%val = trunc <8 x i64> %a to <8 x i8>
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store <8 x i8> %val, <8 x i8>* %dest
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ret void
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}
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define void @store_trunc_v16i64i8(<16 x i64>* %ap, <16 x i8>* %dest) #0 {
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; CHECK-LABEL: store_trunc_v16i64i8:
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; VBITS_GE_1024: ptrue p[[P0:[0-9]+]].d, vl16
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; VBITS_GE_1024-NEXT: ld1d { [[Z0:z[0-9]+]].d }, p0/z, [x0]
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; VBITS_GE_1024-NEXT: st1b { [[Z0]].d }, p[[P0]], [x{{[0-9]+}}]
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; VBITS_GE_1024-NEXT: ret
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%a = load <16 x i64>, <16 x i64>* %ap
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%val = trunc <16 x i64> %a to <16 x i8>
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store <16 x i8> %val, <16 x i8>* %dest
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ret void
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}
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define void @store_trunc_v32i64i8(<32 x i64>* %ap, <32 x i8>* %dest) #0 {
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; CHECK-LABEL: store_trunc_v32i64i8:
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; VBITS_GE_2048: ptrue p[[P0:[0-9]+]].d, vl32
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; VBITS_GE_2048-NEXT: ld1d { [[Z0:z[0-9]+]].d }, p0/z, [x0]
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; VBITS_GE_2048-NEXT: st1b { [[Z0]].d }, p[[P0]], [x{{[0-9]+}}]
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; VBITS_GE_2048-NEXT: ret
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%a = load <32 x i64>, <32 x i64>* %ap
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%val = trunc <32 x i64> %a to <32 x i8>
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store <32 x i8> %val, <32 x i8>* %dest
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ret void
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}
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define void @store_trunc_v8i64i16(<8 x i64>* %ap, <8 x i16>* %dest) #0 {
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; CHECK-LABEL: store_trunc_v8i64i16:
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; VBITS_GE_512: ptrue p[[P0:[0-9]+]].d, vl8
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; VBITS_GE_512-NEXT: ld1d { [[Z0:z[0-9]+]].d }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1h { [[Z0]].d }, p[[P0]], [x{{[0-9]+}}]
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; VBITS_GE_512-NEXT: ret
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; Ensure sensible type legalisation.
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; Currently does not use the truncating store
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; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
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; VBITS_EQ_256-DAG: ld1d { [[Z0:z[0-9]+]].d }, [[PG]]/z, [x8]
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; VBITS_EQ_256-DAG: ld1d { [[Z1:z[0-9]+]].d }, [[PG]]/z, [x0]
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; VBITS_EQ_256-DAG: uzp1 [[Z0]].s, [[Z0]].s, [[Z0]].s
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; VBITS_EQ_256-DAG: uzp1 [[Z1]].s, [[Z1]].s, [[Z1]].s
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; VBITS_EQ_256-DAG: uzp1 [[Z1]].h, [[Z1]].h, [[Z1]].h
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; VBITS_EQ_256-DAG: uzp1 [[Z0]].h, [[Z0]].h, [[Z0]].h
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; VBITS_EQ_256-DAG: mov v[[V0:[0-9]+]].d[1], v{{[0-9]+}}.d[0]
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; VBITS_EQ_256-DAG: str q[[V0]], [x1]
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; VBITS_EQ_256-DAG: ret
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%a = load <8 x i64>, <8 x i64>* %ap
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%val = trunc <8 x i64> %a to <8 x i16>
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store <8 x i16> %val, <8 x i16>* %dest
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ret void
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}
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define void @store_trunc_v8i64i32(<8 x i64>* %ap, <8 x i32>* %dest) #0 {
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; CHECK-LABEL: store_trunc_v8i64i32:
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; VBITS_GE_512: ptrue p[[P0:[0-9]+]].d, vl8
|
||||
; VBITS_GE_512-NEXT: ld1d { [[Z0:z[0-9]+]].d }, p0/z, [x0]
|
||||
; VBITS_GE_512-NEXT: st1w { [[Z0]].d }, p[[P0]], [x{{[0-9]+}}]
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
|
||||
; Ensure sensible type legalisation
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
|
||||
; VBITS_EQ_256-DAG: ld1d { [[Z0:z[0-9]+]].d }, [[PG]]/z, [x8]
|
||||
; VBITS_EQ_256-DAG: ld1d { [[Z1:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG]].s, vl4
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z0]].s, [[Z0]].s, [[Z0]].s
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z1]].s, [[Z1]].s, [[Z1]].s
|
||||
; VBITS_EQ_256-DAG: splice [[Z1]].s, [[PG]], [[Z1]].s, [[Z0]].s
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG]].s, vl8
|
||||
; VBITS_EQ_256-DAG: st1w { [[Z1]].s }, [[PG]], [x1]
|
||||
; VBITS_EQ_256-DAG: ret
|
||||
%a = load <8 x i64>, <8 x i64>* %ap
|
||||
%val = trunc <8 x i64> %a to <8 x i32>
|
||||
store <8 x i32> %val, <8 x i32>* %dest
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_trunc_v16i32i8(<16 x i32>* %ap, <16 x i8>* %dest) #0 {
|
||||
; CHECK-LABEL: store_trunc_v16i32i8:
|
||||
; VBITS_GE_512: ptrue p[[P0:[0-9]+]].s, vl16
|
||||
; VBITS_GE_512-NEXT: ld1w { [[Z0:z[0-9]+]].s }, p0/z, [x0]
|
||||
; VBITS_GE_512-NEXT: st1b { [[Z0]].s }, p[[P0]], [x{{[0-9]+}}]
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
|
||||
; Ensure sensible type legalisation.
|
||||
; Currently does not use the truncating store
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8
|
||||
; VBITS_EQ_256-DAG: ld1w { [[Z0:z[0-9]+]].s }, [[PG]]/z, [x8]
|
||||
; VBITS_EQ_256-DAG: ld1w { [[Z1:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z0]].h, [[Z0]].h, [[Z0]].h
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z1]].h, [[Z1]].h, [[Z1]].h
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z1]].b, [[Z1]].b, [[Z1]].b
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z0]].b, [[Z0]].b, [[Z0]].b
|
||||
; VBITS_EQ_256-DAG: mov v[[V0:[0-9]+]].d[1], v{{[0-9]+}}.d[0]
|
||||
; VBITS_EQ_256-DAG: str q[[V0]], [x1]
|
||||
; VBITS_EQ_256-DAG: ret
|
||||
%a = load <16 x i32>, <16 x i32>* %ap
|
||||
%val = trunc <16 x i32> %a to <16 x i8>
|
||||
store <16 x i8> %val, <16 x i8>* %dest
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_trunc_v16i32i16(<16 x i32>* %ap, <16 x i16>* %dest) #0 {
|
||||
; CHECK-LABEL: store_trunc_v16i32i16:
|
||||
; VBITS_GE_512: ptrue p[[P0:[0-9]+]].s, vl16
|
||||
; VBITS_GE_512-NEXT: ld1w { [[Z0:z[0-9]+]].s }, p0/z, [x0]
|
||||
; VBITS_GE_512-NEXT: st1h { [[Z0]].s }, p[[P0]], [x{{[0-9]+}}]
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
|
||||
; Ensure sensible type legalisation
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8
|
||||
; VBITS_EQ_256-DAG: ld1w { [[Z0:z[0-9]+]].s }, [[PG]]/z, [x8]
|
||||
; VBITS_EQ_256-DAG: ld1w { [[Z1:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG]].h, vl8
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z0]].h, [[Z0]].h, [[Z0]].h
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z1]].h, [[Z1]].h, [[Z1]].h
|
||||
; VBITS_EQ_256-DAG: splice [[Z1]].h, [[PG]], [[Z1]].h, [[Z0]].h
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG]].h, vl16
|
||||
; VBITS_EQ_256-DAG: st1h { [[Z1]].h }, [[PG]], [x1]
|
||||
; VBITS_EQ_256-DAG: ret
|
||||
%a = load <16 x i32>, <16 x i32>* %ap
|
||||
%val = trunc <16 x i32> %a to <16 x i16>
|
||||
store <16 x i16> %val, <16 x i16>* %dest
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_trunc_v32i16i8(<32 x i16>* %ap, <32 x i8>* %dest) #0 {
|
||||
; CHECK-LABEL: store_trunc_v32i16i8:
|
||||
; VBITS_GE_512: ptrue p[[P0:[0-9]+]].h, vl32
|
||||
; VBITS_GE_512-NEXT: ld1h { [[Z0:z[0-9]+]].h }, p0/z, [x0]
|
||||
; VBITS_GE_512-NEXT: st1b { [[Z0]].h }, p[[P0]], [x{{[0-9]+}}]
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
|
||||
; Ensure sensible type legalisation
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16
|
||||
; VBITS_EQ_256-DAG: ld1h { [[Z0:z[0-9]+]].h }, [[PG]]/z, [x8]
|
||||
; VBITS_EQ_256-DAG: ld1h { [[Z1:z[0-9]+]].h }, [[PG]]/z, [x0]
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG]].b, vl16
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z0]].b, [[Z0]].b, [[Z0]].b
|
||||
; VBITS_EQ_256-DAG: uzp1 [[Z1]].b, [[Z1]].b, [[Z1]].b
|
||||
; VBITS_EQ_256-DAG: splice [[Z1]].b, [[PG]], [[Z1]].b, [[Z0]].b
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG]].b, vl32
|
||||
; VBITS_EQ_256-DAG: st1b { [[Z1]].b }, [[PG]], [x1]
|
||||
; VBITS_EQ_256-DAG: ret
|
||||
%a = load <32 x i16>, <32 x i16>* %ap
|
||||
%val = trunc <32 x i16> %a to <32 x i8>
|
||||
store <32 x i8> %val, <32 x i8>* %dest
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
attributes #0 = { "target-features"="+sve" }
|
||||
@ -255,9 +255,10 @@ define dso_local void @g2(%struct.S1* %a) {
|
||||
; N32-NEXT: .cfi_offset 31, -8
|
||||
; N32-NEXT: .cfi_offset 16, -16
|
||||
; N32-NEXT: move $5, $4
|
||||
; N32-NEXT: lui $1, 1
|
||||
; N32-NEXT: addu $1, $sp, $1
|
||||
; N32-NEXT: sw $4, -4($1)
|
||||
; N32-NEXT: sll $1, $5, 0
|
||||
; N32-NEXT: lui $2, 1
|
||||
; N32-NEXT: addu $2, $sp, $2
|
||||
; N32-NEXT: sw $1, -4($2)
|
||||
; N32-NEXT: addiu $16, $sp, 8
|
||||
; N32-NEXT: ori $6, $zero, 65520
|
||||
; N32-NEXT: jal memcpy
|
||||
@ -388,8 +389,10 @@ define dso_local i32 @g3(%struct.S1* %a, %struct.S1* %b) #0 {
|
||||
; N32-NEXT: .cfi_def_cfa_offset 16
|
||||
; N32-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
|
||||
; N32-NEXT: .cfi_offset 31, -8
|
||||
; N32-NEXT: sw $5, 0($sp)
|
||||
; N32-NEXT: sw $4, 4($sp)
|
||||
; N32-NEXT: sll $1, $5, 0
|
||||
; N32-NEXT: sw $1, 0($sp)
|
||||
; N32-NEXT: sll $1, $4, 0
|
||||
; N32-NEXT: sw $1, 4($sp)
|
||||
; N32-NEXT: jal memcpy
|
||||
; N32-NEXT: ori $6, $zero, 65520
|
||||
; N32-NEXT: addiu $2, $zero, 4
|
||||
|
||||
@ -554,8 +554,10 @@ define <4 x i8> @i8_4(<4 x i8> %a, <4 x i8> %b) {
|
||||
; MIPS64R5: # %bb.0:
|
||||
; MIPS64R5-NEXT: daddiu $sp, $sp, -16
|
||||
; MIPS64R5-NEXT: .cfi_def_cfa_offset 16
|
||||
; MIPS64R5-NEXT: sw $5, 8($sp)
|
||||
; MIPS64R5-NEXT: sw $4, 12($sp)
|
||||
; MIPS64R5-NEXT: sll $1, $5, 0
|
||||
; MIPS64R5-NEXT: sw $1, 8($sp)
|
||||
; MIPS64R5-NEXT: sll $1, $4, 0
|
||||
; MIPS64R5-NEXT: sw $1, 12($sp)
|
||||
; MIPS64R5-NEXT: lbu $1, 9($sp)
|
||||
; MIPS64R5-NEXT: lbu $2, 8($sp)
|
||||
; MIPS64R5-NEXT: insert.w $w0[0], $2
|
||||
@ -1261,8 +1263,10 @@ define <2 x i16> @i16_2(<2 x i16> %a, <2 x i16> %b) {
|
||||
; MIPS64R5: # %bb.0:
|
||||
; MIPS64R5-NEXT: daddiu $sp, $sp, -16
|
||||
; MIPS64R5-NEXT: .cfi_def_cfa_offset 16
|
||||
; MIPS64R5-NEXT: sw $5, 8($sp)
|
||||
; MIPS64R5-NEXT: sw $4, 12($sp)
|
||||
; MIPS64R5-NEXT: sll $1, $5, 0
|
||||
; MIPS64R5-NEXT: sw $1, 8($sp)
|
||||
; MIPS64R5-NEXT: sll $1, $4, 0
|
||||
; MIPS64R5-NEXT: sw $1, 12($sp)
|
||||
; MIPS64R5-NEXT: lh $1, 10($sp)
|
||||
; MIPS64R5-NEXT: lh $2, 8($sp)
|
||||
; MIPS64R5-NEXT: insert.d $w0[0], $2
|
||||
|
||||
@ -285,57 +285,65 @@ define void @f3(i32 %a) {
|
||||
;
|
||||
; MIPS4-LABEL: f3:
|
||||
; MIPS4: # %bb.0:
|
||||
; MIPS4-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
|
||||
; MIPS4-NEXT: sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Imm:0>>
|
||||
; MIPS4-NEXT: lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Expr:(%highest(c))>>
|
||||
; MIPS4-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
|
||||
; MIPS4-NEXT: daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Expr:(%higher(c))>>
|
||||
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
|
||||
; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Imm:16>>
|
||||
; MIPS4-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
|
||||
; MIPS4-NEXT: daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Expr:(%hi(c))>>
|
||||
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
|
||||
; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Imm:16>>
|
||||
; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MIPS4-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
|
||||
; MIPS4-NEXT: sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS4-NEXT: # <MCOperand Expr:(%lo(c))>>
|
||||
;
|
||||
; MIPS64R6-LABEL: f3:
|
||||
; MIPS64R6: # %bb.0:
|
||||
; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
|
||||
; MIPS64R6-NEXT: sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Imm:0>>
|
||||
; MIPS64R6-NEXT: lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
|
||||
; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
|
||||
; MIPS64R6-NEXT: daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
|
||||
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
|
||||
; MIPS64R6-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
|
||||
; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
|
||||
; MIPS64R6-NEXT: daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
|
||||
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
|
||||
; MIPS64R6-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
|
||||
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
|
||||
; MIPS64R6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
|
||||
; MIPS64R6-NEXT: sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
|
||||
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user