mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 05:01:59 +01:00
[Hexagon] Handle cases when the aligned stack pointer is missing
llvm-svn: 306288
This commit is contained in:
Krzysztof Parzyszek
parent
12cce93ec7
commit
f30628d6b1
@ -1051,10 +1051,26 @@ int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF,
|
||||
bool HasExtraAlign = HRI.needsStackRealignment(MF);
|
||||
bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
|
||||
|
||||
unsigned FrameSize = MFI.getStackSize();
|
||||
unsigned SP = HRI.getStackRegister(), FP = HRI.getFrameRegister();
|
||||
auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
|
||||
unsigned AP = HMFI.getStackAlignBasePhysReg();
|
||||
unsigned FrameSize = MFI.getStackSize();
|
||||
// It may happen that AP will be absent even HasAlloca && HasExtraAlign
|
||||
// is true. HasExtraAlign may be set because of vector spills, without
|
||||
// aligned locals or aligned outgoing function arguments. Since vector
|
||||
// spills will ultimately be "unaligned", it is safe to use FP as the
|
||||
// base register.
|
||||
// In fact, in such a scenario the stack is actually not required to be
|
||||
// aligned, although it may end up being aligned anyway, since this
|
||||
// particular case is not easily detectable. The alignment will be
|
||||
// unnecessary, but not incorrect.
|
||||
// Unfortunately there is no quick way to verify that the above is
|
||||
// indeed the case (and that it's not a result of an error), so just
|
||||
// assume that missing AP will be replaced by FP.
|
||||
// (A better fix would be to rematerialize AP from FP and always align
|
||||
// vector spills.)
|
||||
if (AP == 0)
|
||||
AP = FP;
|
||||
|
||||
bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
|
||||
// Use FP at -O0, except when there are objects with extra alignment.
|
||||
|
||||
@ -94,10 +94,6 @@ static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
|
||||
///
|
||||
/// Constants for Hexagon instructions.
|
||||
///
|
||||
const int Hexagon_MEMV_OFFSET_MAX_128B = 896; // #s4: -8*128...7*128
|
||||
const int Hexagon_MEMV_OFFSET_MIN_128B = -1024; // #s4
|
||||
const int Hexagon_MEMV_OFFSET_MAX = 448; // #s4: -8*64...7*64
|
||||
const int Hexagon_MEMV_OFFSET_MIN = -512; // #s4
|
||||
const int Hexagon_MEMW_OFFSET_MAX = 4095;
|
||||
const int Hexagon_MEMW_OFFSET_MIN = -4096;
|
||||
const int Hexagon_MEMD_OFFSET_MAX = 8191;
|
||||
@ -2443,8 +2439,7 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
|
||||
case Hexagon::V6_vS32b_ai:
|
||||
case Hexagon::V6_vL32Ub_ai:
|
||||
case Hexagon::V6_vS32Ub_ai:
|
||||
return (Offset >= Hexagon_MEMV_OFFSET_MIN) &&
|
||||
(Offset <= Hexagon_MEMV_OFFSET_MAX);
|
||||
return isShiftedInt<4,6>(Offset);
|
||||
|
||||
case Hexagon::PS_vstorerq_ai_128B:
|
||||
case Hexagon::PS_vstorerw_ai_128B:
|
||||
@ -2454,8 +2449,7 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
|
||||
case Hexagon::V6_vS32b_ai_128B:
|
||||
case Hexagon::V6_vL32Ub_ai_128B:
|
||||
case Hexagon::V6_vS32Ub_ai_128B:
|
||||
return (Offset >= Hexagon_MEMV_OFFSET_MIN_128B) &&
|
||||
(Offset <= Hexagon_MEMV_OFFSET_MAX_128B);
|
||||
return isShiftedInt<4,7>(Offset);
|
||||
|
||||
case Hexagon::J2_loop0i:
|
||||
case Hexagon::J2_loop1i:
|
||||
|
||||
51
test/CodeGen/Hexagon/stack-align-reset.ll
Normal file
51
test/CodeGen/Hexagon/stack-align-reset.ll
Normal file
@ -0,0 +1,51 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
;
|
||||
; This used to crash.
|
||||
; CHECK: call f1
|
||||
|
||||
target triple = "hexagon-unknown--elf"
|
||||
|
||||
%struct.0 = type { [5 x i32] }
|
||||
%struct.2 = type { i32, i32, i32, %struct.1* }
|
||||
%struct.1 = type { i16*, i32, i32, i32 }
|
||||
|
||||
@g0 = external hidden unnamed_addr constant [52 x i8], align 1
|
||||
@g1 = external hidden unnamed_addr constant [3 x i8], align 1
|
||||
|
||||
declare extern_weak void @f0(i32, i8*, i32, i8*, ...) #0
|
||||
declare void @f1(%struct.0*, i32) #0
|
||||
|
||||
define void @fred(i8* %a0) #0 {
|
||||
b1:
|
||||
%v2 = alloca %struct.0, align 4
|
||||
%v3 = alloca %struct.2, i32 undef, align 8
|
||||
br i1 undef, label %b5, label %b4
|
||||
|
||||
b4: ; preds = %b1
|
||||
br label %b7
|
||||
|
||||
b5: ; preds = %b5, %b1
|
||||
%v6 = getelementptr inbounds %struct.2, %struct.2* %v3, i32 undef, i32 3
|
||||
store %struct.1* undef, %struct.1** %v6, align 4
|
||||
br label %b5
|
||||
|
||||
b7: ; preds = %b10, %b4
|
||||
%v8 = call i32 @llvm.hexagon.V6.extractw(<16 x i32> zeroinitializer, i32 0)
|
||||
br i1 icmp eq (void (i32, i8*, i32, i8*, ...)* @f0, void (i32, i8*, i32, i8*, ...)* null), label %b11, label %b9
|
||||
|
||||
b9: ; preds = %b7
|
||||
call void (i32, i8*, i32, i8*, ...) @f0(i32 2, i8* getelementptr inbounds ([52 x i8], [52 x i8]* @g0, i32 0, i32 0), i32 2346, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @g1, i32 0, i32 0), i32 %v8)
|
||||
unreachable
|
||||
|
||||
b10: ; preds = %b11
|
||||
call void @f1(%struct.0* nonnull %v2, i32 28)
|
||||
br label %b7
|
||||
|
||||
b11: ; preds = %b11, %b7
|
||||
br i1 undef, label %b10, label %b11
|
||||
}
|
||||
|
||||
declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
30
test/CodeGen/Hexagon/vec-vararg-align.ll
Normal file
30
test/CodeGen/Hexagon/vec-vararg-align.ll
Normal file
@ -0,0 +1,30 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
;
|
||||
; Check that the stack is aligned according to the outgoing function arguments.
|
||||
; CHECK: r29 = and(r29,#-128)
|
||||
|
||||
target triple = "hexagon-unknown--elf"
|
||||
|
||||
@.str = private unnamed_addr constant [32 x i8] c"\0AMixed Vectors, Pairs, int flt\0A\00", align 1
|
||||
@.str.1 = private unnamed_addr constant [11 x i8] c"\0AVar args\0A\00", align 1
|
||||
@gVec0 = common global <16 x i32> zeroinitializer, align 64
|
||||
@gVec10 = common global <32 x i32> zeroinitializer, align 128
|
||||
@gi1 = common global i32 0, align 4
|
||||
@gf1 = common global float 0.000000e+00, align 4
|
||||
|
||||
define i32 @main() #0 {
|
||||
b0:
|
||||
%v1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0)) #0
|
||||
%v2 = load <16 x i32>, <16 x i32>* @gVec0, align 64
|
||||
%v3 = load <32 x i32>, <32 x i32>* @gVec10, align 128
|
||||
%v4 = load i32, i32* @gi1, align 4
|
||||
%v5 = load float, float* @gf1, align 4
|
||||
%v6 = fpext float %v5 to double
|
||||
call void (i8*, i32, ...) @VarVec1(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str.1, i32 0, i32 0), i32 4, <16 x i32> %v2, <32 x i32> %v3, i32 %v4, double %v6)
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
declare i32 @printf(i8*, ...) #0
|
||||
declare void @VarVec1(i8*, i32, ...) #0
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
|
||||
Loading…
x
Reference in New Issue
Block a user