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Fixups for Thumb2 vldr's need to have the effective PC aligned as well.

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llvm-svn: 121587
This commit is contained in:
Owen Anderson 2010-12-10 22:46:47 +00:00
parent 7f1cea7009
commit f310c92333
2 changed files with 4 additions and 3 deletions
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4
lib/Target/ARM/ARMAsmBackend.cpp
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@ -207,12 +207,12 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
// Offset by 4 and don't encode the lower bit, which is always 0.
return ((Value - 4) >> 1) & 0xff;
case ARM::fixup_arm_pcrel_10:
Value = Value - 6; // ARM fixups offset by an additional word and don't
Value = Value - 4; // ARM fixups offset by an additional word and don't
// need to adjust for the half-word ordering.
// Fall through.
case ARM::fixup_t2_pcrel_10: {
// Offset by 4, adjusted by two due to the half-word ordering of thumb.
Value = Value - 2;
Value = Value - 4;
bool isAdd = true;
if ((int64_t)Value < 0) {
Value = -Value;

3
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -53,7 +53,8 @@ public:
{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAligned},
{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel |