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[Hexagon] Only process bitcasts of vsplats when selecting const vectors

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Selecting of constant HVX vectors involves some "manual processing",
which mishandled an unrelated BITCAST operation causing a selection
error.

llvm-svn: 323887
This commit is contained in:
Krzysztof Parzyszek 2018-01-31 16:48:20 +00:00
parent dd97f56777
commit f31df17b9d
2 changed files with 43 additions and 1 deletions
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7
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
View File

@ -926,8 +926,13 @@ bool HvxSelector::selectVectorConstants(SDNode *N) {
if (N->isMachineOpcode())
return false;
unsigned Opc = N->getOpcode();
if (Opc == HexagonISD::VSPLAT || Opc == ISD::BITCAST)
if (Opc == HexagonISD::VSPLAT)
return true;
if (Opc == ISD::BITCAST) {
// Only select bitcasts of VSPLATs.
if (N->getOperand(0).getOpcode() == HexagonISD::VSPLAT)
return true;
}
if (Opc == ISD::LOAD) {
SDValue Addr = cast<LoadSDNode>(N)->getBasePtr();
unsigned AddrOpc = Addr.getOpcode();

37
test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll Normal file
View File

@ -0,0 +1,37 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; The generation of a constant vector in the selection step resulted in
; a VSPLAT, which, deeper in the expression tree had an unrelated BITCAST.
; That bitcast was erroneously removed by the constant vector selection
; function, and caused a selection error due to a type mismatch.
;
; Make sure this compiles successfully.
; CHECK: vsplat
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define void @fred() #0 {
b0:
%v1 = load <8 x i16>, <8 x i16>* undef, align 2
%v2 = icmp sgt <8 x i16> %v1, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
%v3 = zext <8 x i1> %v2 to <8 x i32>
%v4 = add nuw nsw <8 x i32> zeroinitializer, %v3
%v5 = add nuw nsw <8 x i32> %v4, zeroinitializer
%v6 = shufflevector <8 x i32> %v5, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%v7 = add nuw nsw <8 x i32> %v5, %v6
%v8 = extractelement <8 x i32> %v7, i32 0
%v9 = add nuw nsw i32 %v8, 0
%v10 = add nuw nsw i32 %v9, 0
%v11 = add nuw nsw i32 %v10, 0
%v12 = icmp ult i32 %v11, 5
br i1 %v12, label %b13, label %b14
b13: ; preds = %b0
unreachable
b14: ; preds = %b0
ret void
}
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }