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[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
Avoid having to round up to v8f32/VReg_256 when only 5 VGPRs are required for a MIMG address operand. Maintain _V8 instruction variants of pseudo instructions allowing assembly prior to GFX10 to work as-is. Currently the validator can tell for GFX10 what the correct size is, so will disallow oversize address registers. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D103672
This commit is contained in:
Carl Ritson
parent
89d484d4dd
commit
f3236bf71f
@ -3445,7 +3445,7 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst) {
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if (!IsNSA) {
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if (AddrSize > 8)
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AddrSize = 16;
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else if (AddrSize > 4)
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else if (AddrSize > 5)
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AddrSize = 8;
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}
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@ -730,7 +730,7 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
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if (!IsNSA) {
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if (AddrSize > 8)
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AddrSize = 16;
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else if (AddrSize > 4)
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else if (AddrSize > 5)
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AddrSize = 8;
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} else {
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if (AddrSize > Info->VAddrDwords) {
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@ -713,8 +713,9 @@ class MIMGAddrSize<int dw, bit enable_disasm> {
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!if(!eq(NumWords, 2), VReg_64,
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!if(!eq(NumWords, 3), VReg_96,
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!if(!eq(NumWords, 4), VReg_128,
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!if(!eq(NumWords, 5), VReg_160,
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!if(!le(NumWords, 8), VReg_256,
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!if(!le(NumWords, 16), VReg_512, ?)))))));
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!if(!le(NumWords, 16), VReg_512, ?))))))));
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// Whether the instruction variant with this vaddr size should be enabled for
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// the auto-generated disassembler.
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@ -755,11 +756,12 @@ class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
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// required numbers of address words. The disassembler defaults to the
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// smallest register class.
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list<MIMGAddrSize> MachineInstrs =
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!foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 8, 16], lhs, dw,
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!foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 5, 8, 16], lhs, dw,
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!if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret,
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MIMGAddrSizes_tmp<
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!listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]),
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!if(!eq(dw, 3), 3, !add(dw, 1))>, // we still need _V4 for codegen w/ 3 dwords
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!if(!or(!eq(dw, 3), !eq(dw, 5)), dw, !add(dw, 1))>,
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// we still want _V4/_V8 for codegen with 3/5 dwords
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lhs)).List;
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// For NSA, generate machine instructions for all possible numbers of words
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@ -5821,6 +5821,9 @@ static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
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} else if (Elts.size() <= 4) {
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Type = MVT::v4f32;
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NumElts = 4;
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} else if (Elts.size() <= 5) {
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Type = MVT::v5f32;
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NumElts = 5;
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} else if (Elts.size() <= 8) {
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Type = MVT::v8f32;
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NumElts = 8;
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@ -4233,12 +4233,8 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
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VAddrWords = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 32;
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if (AddrWords > 8)
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AddrWords = 16;
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else if (AddrWords > 4)
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else if (AddrWords > 5)
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AddrWords = 8;
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else if (AddrWords == 4)
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AddrWords = 4;
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else if (AddrWords == 3)
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AddrWords = 3;
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}
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if (VAddrWords != AddrWords) {
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@ -232,6 +232,8 @@ void SIShrinkInstructions::shrinkMIMG(MachineInstr &MI) {
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RC = &AMDGPU::VReg_96RegClass;
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} else if (Info->VAddrDwords == 4) {
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RC = &AMDGPU::VReg_128RegClass;
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} else if (Info->VAddrDwords == 5) {
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RC = &AMDGPU::VReg_160RegClass;
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} else if (Info->VAddrDwords <= 8) {
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RC = &AMDGPU::VReg_256RegClass;
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NewAddrDwords = 8;
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@ -526,7 +526,7 @@ define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX10NSA-NEXT: s_mov_b32 s9, s11
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; GFX10NSA-NEXT: s_mov_b32 s10, s12
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; GFX10NSA-NEXT: s_mov_b32 s11, s13
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; GFX10NSA-NEXT: image_gather4_c_b_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10NSA-NEXT: image_gather4_c_b_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
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; GFX10NSA-NEXT: ; return to shader part epilog
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main_body:
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@ -182,7 +182,7 @@ define amdgpu_ps <4 x float> @gather4_c_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX10-NEXT: s_mov_b32 s9, s11
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; GFX10-NEXT: s_mov_b32 s10, s12
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; GFX10-NEXT: s_mov_b32 s11, s13
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; GFX10-NEXT: image_gather4_c_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: image_gather4_c_cl_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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@ -276,7 +276,7 @@ define amdgpu_ps <4 x float> @gather4_c_b_o_2d(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX10-NEXT: s_mov_b32 s9, s11
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; GFX10-NEXT: s_mov_b32 s10, s12
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; GFX10-NEXT: s_mov_b32 s11, s13
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; GFX10-NEXT: image_gather4_c_b_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: image_gather4_c_b_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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@ -317,7 +317,7 @@ define amdgpu_ps <4 x float> @gather4_b_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX10-NEXT: s_mov_b32 s9, s11
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; GFX10-NEXT: s_mov_b32 s10, s12
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; GFX10-NEXT: s_mov_b32 s11, s13
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; GFX10-NEXT: image_gather4_b_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: image_gather4_b_cl_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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@ -446,7 +446,7 @@ define amdgpu_ps <4 x float> @gather4_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX10-NEXT: s_mov_b32 s9, s11
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; GFX10-NEXT: s_mov_b32 s10, s12
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; GFX10-NEXT: s_mov_b32 s11, s13
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; GFX10-NEXT: image_gather4_c_l_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: image_gather4_c_l_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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@ -120,7 +120,7 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX10-NEXT: s_lshl_b32 s12, s0, 16
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; GFX10-NEXT: v_and_or_b32 v1, v1, v5, s12
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; GFX10-NEXT: v_and_or_b32 v2, v2, v5, s12
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; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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@ -244,7 +244,7 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX10-NEXT: s_lshl_b32 s12, s0, 16
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; GFX10-NEXT: v_and_or_b32 v1, v1, v5, s12
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; GFX10-NEXT: v_and_or_b32 v2, v2, v5, s12
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; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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@ -99,8 +99,8 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_b_cl_2d:
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; GFX6789: image_gather4_c_b_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX10: image_gather4_c_b_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
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; GFX6789: image_gather4_c_b_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1{{$}}
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; GFX10: image_gather4_c_b_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ;
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define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, float %s, float %t, float %clamp) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f32(i32 1, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -26,7 +26,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_cl_o_2d:
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; GCN: image_gather4_c_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1{{$}}
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; GCN: image_gather4_c_cl_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1{{$}}
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define amdgpu_ps <4 x float> @gather4_c_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %clamp) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -42,7 +42,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_b_o_2d:
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; GCN: image_gather4_c_b_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1{{$}}
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; GCN: image_gather4_c_b_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1{{$}}
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define amdgpu_ps <4 x float> @gather4_c_b_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %zcompare, float %s, float %t) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -50,7 +50,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_b_cl_o_2d:
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; GCN: image_gather4_b_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1{{$}}
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; GCN: image_gather4_b_cl_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1{{$}}
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define amdgpu_ps <4 x float> @gather4_b_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %s, float %t, float %clamp) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -74,7 +74,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_l_o_2d:
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; GCN: image_gather4_c_l_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1{{$}}
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; GCN: image_gather4_c_l_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1{{$}}
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define amdgpu_ps <4 x float> @gather4_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -32,8 +32,8 @@ main_body:
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}
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; GCN-LABEL: {{^}}sample_contig_nsa:
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; NONSA: image_sample_c_l v5, v[0:7],
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; NSA: image_sample_c_l v8, v[0:7],
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; NONSA: image_sample_c_l v5, v[0:4],
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; NSA: image_sample_c_l v8, v[0:4],
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; NSA: image_sample v9, [v6, v7, v5],
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define amdgpu_ps <2 x float> @sample_contig_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {
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main_body:
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@ -69,9 +69,9 @@ main_body:
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}
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; GCN-LABEL: {{^}}sample_contig_contig:
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; NSA: image_sample_c_l v8, v[0:7],
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; NSA: image_sample_c_l v8, v[0:4],
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; NSA: image_sample v9, v[5:7],
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; NONSA: image_sample_c_l v8, v[0:7],
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; NONSA: image_sample_c_l v8, v[0:4],
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; NONSA: image_sample v9, v[5:7],
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define amdgpu_ps <2 x float> @sample_contig_contig(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %s2, float %t2, float %r2) {
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main_body:
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@ -750,7 +750,7 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX9-NEXT: v_lshl_or_b32 v10, v6, 16, v5
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; GFX9-NEXT: v_lshl_or_b32 v9, v4, 16, v3
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; GFX9-NEXT: v_lshl_or_b32 v8, v2, 16, v0
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; GFX9-NEXT: image_sample_c_d_cl v[0:3], v[7:14], s[0:7], s[8:11] dmask:0xf a16
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; GFX9-NEXT: image_sample_c_d_cl v[0:3], v[7:11], s[0:7], s[8:11] dmask:0xf a16
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: ; return to shader part epilog
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;
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@ -954,7 +954,7 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX9-NEXT: v_lshl_or_b32 v10, v6, 16, v5
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; GFX9-NEXT: v_lshl_or_b32 v9, v4, 16, v3
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; GFX9-NEXT: v_lshl_or_b32 v8, v2, 16, v0
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; GFX9-NEXT: image_sample_c_cd_cl v[0:3], v[7:14], s[0:7], s[8:11] dmask:0xf a16
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; GFX9-NEXT: image_sample_c_cd_cl v[0:3], v[7:11], s[0:7], s[8:11] dmask:0xf a16
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: ; return to shader part epilog
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;
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@ -1108,7 +1108,7 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
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; VERDE-NEXT: s_mov_b64 s[12:13], exec
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; VERDE-NEXT: s_wqm_b64 exec, exec
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; VERDE-NEXT: s_and_b64 exec, exec, s[12:13]
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; VERDE-NEXT: image_sample_c_b_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
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; VERDE-NEXT: image_sample_c_b_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf
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; VERDE-NEXT: s_waitcnt vmcnt(0)
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; VERDE-NEXT: ; return to shader part epilog
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;
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@ -1117,7 +1117,7 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
|
||||
; GFX6789-NEXT: s_mov_b64 s[12:13], exec
|
||||
; GFX6789-NEXT: s_wqm_b64 exec, exec
|
||||
; GFX6789-NEXT: s_and_b64 exec, exec, s[12:13]
|
||||
; GFX6789-NEXT: image_sample_c_b_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: image_sample_c_b_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX6789-NEXT: ; return to shader part epilog
|
||||
;
|
||||
@ -1126,7 +1126,7 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
|
||||
; GFX10-NEXT: s_mov_b32 s12, exec_lo ; encoding: [0x7e,0x03,0x8c,0xbe]
|
||||
; GFX10-NEXT: s_wqm_b32 exec_lo, exec_lo ; encoding: [0x7e,0x09,0xfe,0xbe]
|
||||
; GFX10-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; encoding: [0x7e,0x0c,0x7e,0x87]
|
||||
; GFX10-NEXT: image_sample_c_b_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xb8,0xf0,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: image_sample_c_b_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xb8,0xf0,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
@ -1275,19 +1275,19 @@ main_body:
|
||||
define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp) {
|
||||
; VERDE-LABEL: sample_c_d_cl_1d:
|
||||
; VERDE: ; %bb.0: ; %main_body
|
||||
; VERDE-NEXT: image_sample_c_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: image_sample_c_d_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: s_waitcnt vmcnt(0)
|
||||
; VERDE-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX6789-LABEL: sample_c_d_cl_1d:
|
||||
; GFX6789: ; %bb.0: ; %main_body
|
||||
; GFX6789-NEXT: image_sample_c_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: image_sample_c_d_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX6789-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: sample_c_d_cl_1d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: image_sample_c_d_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
@ -1459,19 +1459,19 @@ main_body:
|
||||
define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp) {
|
||||
; VERDE-LABEL: sample_c_cd_cl_1d:
|
||||
; VERDE: ; %bb.0: ; %main_body
|
||||
; VERDE-NEXT: image_sample_c_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: image_sample_c_cd_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: s_waitcnt vmcnt(0)
|
||||
; VERDE-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX6789-LABEL: sample_c_cd_cl_1d:
|
||||
; GFX6789: ; %bb.0: ; %main_body
|
||||
; GFX6789-NEXT: image_sample_c_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: image_sample_c_cd_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX6789-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: sample_c_cd_cl_1d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: image_sample_c_cd_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
||||
@ -28,7 +28,7 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
||||
; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
||||
; GFX10-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10-NEXT: image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
;
|
||||
@ -36,7 +36,7 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
|
||||
; GFX10GISEL: ; %bb.0: ; %main_body
|
||||
; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v4, v5
|
||||
; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
@ -222,7 +222,7 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
||||
; GFX10-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
||||
; GFX10-NEXT: image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10-NEXT: image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
;
|
||||
@ -230,7 +230,7 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
|
||||
; GFX10GISEL: ; %bb.0: ; %main_body
|
||||
; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v4, 0xffff, v4, v5
|
||||
; GFX10GISEL-NEXT: image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
@ -615,7 +615,7 @@ main_body:
|
||||
define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
|
||||
; GFX10-LABEL: sample_g16_noa16_c_d_cl_1d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
;
|
||||
@ -625,7 +625,7 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_d_cl_1d(<8 x i32> inreg %rsrc,
|
||||
; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v5, s12
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v2, v2, v5, s12
|
||||
; GFX10GISEL-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10GISEL-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
@ -807,7 +807,7 @@ main_body:
|
||||
define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
|
||||
; GFX10-LABEL: sample_g16_noa16_c_cd_cl_1d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
;
|
||||
@ -817,7 +817,7 @@ define amdgpu_ps <4 x float> @sample_g16_noa16_c_cd_cl_1d(<8 x i32> inreg %rsrc,
|
||||
; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v1, v1, v5, s12
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v2, v2, v5, s12
|
||||
; GFX10GISEL-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10GISEL-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
||||
@ -101,7 +101,7 @@ main_body:
|
||||
define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
|
||||
; GFX10-LABEL: sample_c_d_cl_1d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
@ -209,7 +209,7 @@ main_body:
|
||||
define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
|
||||
; GFX10-LABEL: sample_c_cd_cl_1d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
||||
@ -101,7 +101,7 @@ main_body:
|
||||
define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
|
||||
; GFX10-LABEL: sample_c_d_cl_1d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10-NEXT: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
@ -209,7 +209,7 @@ main_body:
|
||||
define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {
|
||||
; GFX10-LABEL: sample_c_cd_cl_1d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10-NEXT: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
||||
@ -58,7 +58,7 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_cl_o_2d:
|
||||
; GCN: image_sample_c_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_cl_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %clamp) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
@ -90,7 +90,7 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_b_o_2d:
|
||||
; GCN: image_sample_c_b_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_b_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_b_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %zcompare, float %s, float %t) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f32.f32(i32 15, i32 %offset, float %bias, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
@ -106,7 +106,7 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_b_cl_o_2d:
|
||||
; GCN: image_sample_b_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_b_cl_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_b_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %s, float %t, float %clamp) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.o.2d.v4f32.f32.f32(i32 15, i32 %offset, float %bias, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
@ -114,7 +114,7 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_b_cl_o_1d:
|
||||
; GCN: image_sample_c_b_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_b_cl_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_b_cl_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %zcompare, float %s, float %clamp) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %bias, float %zcompare, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
@ -146,7 +146,7 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_d_o_1d:
|
||||
; GCN: image_sample_c_d_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_d_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_d_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
@ -162,7 +162,7 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_d_cl_o_1d:
|
||||
; GCN: image_sample_d_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_d_cl_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_d_cl_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
@ -210,7 +210,7 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_cd_o_1d:
|
||||
; GCN: image_sample_c_cd_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_cd_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_cd_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
@ -226,7 +226,7 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cd_cl_o_1d:
|
||||
; GCN: image_sample_cd_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_cd_cl_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cd_cl_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
@ -282,7 +282,7 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_l_o_2d:
|
||||
; GCN: image_sample_c_l_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_l_o v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: nsa_reassign
|
||||
# GCN: IMAGE_SAMPLE_C_L_V1_V8_gfx10
|
||||
# GCN: IMAGE_SAMPLE_C_L_V1_V5_gfx10
|
||||
---
|
||||
name: nsa_reassign
|
||||
tracksRegLiveness: true
|
||||
|
||||
@ -21,7 +21,7 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
|
||||
; GFX9-NEXT: v_mov_b32_e32 v32, v12
|
||||
; GFX9: ;;#ASMSTART
|
||||
; GFX9-NEXT: ;;#ASMEND
|
||||
; GFX9: image_gather4_c_b_cl v[40:43], v[32:39], s[4:11], s[4:7] dmask:0x1
|
||||
; GFX9: image_gather4_c_b_cl v[40:43], v[32:36], s[4:11], s[4:7] dmask:0x1
|
||||
; GFX9-NEXT: s_getpc_b64 s[4:5]
|
||||
; GFX9-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4
|
||||
; GFX9-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12
|
||||
@ -53,7 +53,7 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
|
||||
; GFX10: ;;#ASMSTART
|
||||
; GFX10-NEXT: ;;#ASMEND
|
||||
|
||||
; GFX10: image_gather4_c_b_cl v[40:43], v[32:39], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
|
||||
; GFX10: image_gather4_c_b_cl v[40:43], v[32:36], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
|
||||
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX10-NEXT: s_getpc_b64 s[4:5]
|
||||
; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4
|
||||
@ -86,7 +86,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
|
||||
; The upper 3 sub-registers are unused.
|
||||
|
||||
; GFX9-LABEL: call_preserved_vgpr_tuple8:
|
||||
; GFX9: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
||||
; GFX9: buffer_store_dword v45, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
||||
; GFX9: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
|
||||
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
|
||||
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
|
||||
@ -99,7 +99,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
|
||||
; GFX9-NEXT: v_mov_b32_e32 v41, v13
|
||||
; GFX9-NEXT: v_mov_b32_e32 v40, v12
|
||||
|
||||
; GFX9: image_gather4_c_b_cl v[0:3], v[40:47], s[36:43], s[4:7] dmask:0x1
|
||||
; GFX9: image_gather4_c_b_cl v[0:3], v[40:44], s[36:43], s[4:7] dmask:0x1
|
||||
; GFX9-NEXT: s_getpc_b64 s[4:5]
|
||||
; GFX9-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4
|
||||
; GFX9-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12
|
||||
@ -108,7 +108,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
|
||||
; GFX9-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
|
||||
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
|
||||
; GFX9-NEXT: image_gather4_c_b_cl v[0:3], v[40:47], s[36:43], s[4:7] dmask:0x1
|
||||
; GFX9-NEXT: image_gather4_c_b_cl v[0:3], v[40:44], s[36:43], s[4:7] dmask:0x1
|
||||
|
||||
; GFX9: buffer_load_dword v44, off, s[0:3], s33 ; 4-byte Folded Reload
|
||||
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
|
||||
@ -116,7 +116,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
|
||||
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
|
||||
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
|
||||
|
||||
; GFX9: buffer_load_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
||||
; GFX9: buffer_load_dword v45, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
||||
; GFX9: s_setpc_b64 s[4:5]
|
||||
;
|
||||
; GFX10-LABEL: call_preserved_vgpr_tuple8:
|
||||
@ -128,7 +128,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
|
||||
; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill
|
||||
|
||||
|
||||
; GFX10: image_gather4_c_b_cl v[0:3], v[12:19], s[36:43], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
|
||||
; GFX10: image_gather4_c_b_cl v[0:3], v[12:16], s[36:43], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
|
||||
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
||||
; GFX10-NEXT: s_getpc_b64 s[4:5]
|
||||
; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4
|
||||
|
||||
@ -415,8 +415,8 @@ image_load v[1:3], v1, s[16:23] dmask:0x5 dim:SQ_RSRC_IMG_2D a16 tfe lwe
|
||||
image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
|
||||
; GFX10: image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40]
|
||||
|
||||
image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40]
|
||||
image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10: image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40]
|
||||
|
||||
image_sample_d v[0:3], [v0, v1, v2, v3, v4, v5, v6, v8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16
|
||||
; GFX10: image_sample_d v[0:3], [v0, v1, v2, v3, v4, v5, v6, v8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x14,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40,0x01,0x02,0x03,0x04,0x05,0x06,0x08,0x00]
|
||||
@ -442,8 +442,8 @@ image_sample_c_d_cl v[0:3], [v0, v1, v2, v3, v4, v5, v7], s[0:7], s[8:11] dmask:
|
||||
image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
|
||||
; GFX10: image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x40]
|
||||
|
||||
image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10: image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x40]
|
||||
image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10: image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x40]
|
||||
|
||||
image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
|
||||
; GFX10: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40]
|
||||
@ -490,8 +490,8 @@ image_sample_d_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_
|
||||
image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
||||
; GFX10: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0b,0x0f,0x8c,0xf0,0x00,0x00,0x40,0x00,0x02,0x04,0x05,0x06]
|
||||
|
||||
image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00]
|
||||
image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00]
|
||||
|
||||
image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
||||
; GFX10: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0d,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00,0x01,0x03,0x05,0x06,0x07,0x00,0x00,0x00]
|
||||
@ -514,8 +514,8 @@ image_sample_cd_cl_g16 v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG
|
||||
image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
||||
; GFX10: image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0b,0x0f,0xa4,0xf1,0x00,0x00,0x40,0x00,0x02,0x04,0x05,0x06]
|
||||
|
||||
image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00]
|
||||
image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
||||
; GFX10: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00]
|
||||
|
||||
image_sample_c_cd_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
||||
; GFX10: image_sample_c_cd_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0d,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00,0x01,0x03,0x05,0x06,0x07,0x00,0x00,0x00]
|
||||
|
||||
@ -252,7 +252,7 @@
|
||||
# GFX10: image_sample_c_l v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x0f,0xb0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
|
||||
0x1a,0x0f,0xb0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
|
||||
|
||||
# GFX10: image_sample_c_b v[16:19], v[8:15], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03]
|
||||
# GFX10: image_sample_c_b v[16:19], v[8:12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03]
|
||||
0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03
|
||||
|
||||
# TODO: address of this instruction is v[250:255], but this register class does
|
||||
|
||||
@ -111,7 +111,7 @@
|
||||
# GFX10: image_sample_d v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40]
|
||||
0x00,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40
|
||||
|
||||
# GFX10: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40]
|
||||
# GFX10: image_sample_d v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40]
|
||||
0x08,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40
|
||||
|
||||
# GFX10: image_sample_d v[0:3], [v0, v1, v2, v3, v4, v5, v6, v8], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; encoding: [0x14,0x0f,0x88,0xf0,0x00,0x00,0x40,0x40,0x01,0x02,0x03,0x04,0x05,0x06,0x08,0x00]
|
||||
@ -138,7 +138,7 @@
|
||||
# GFX10: image_sample_cd v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x40]
|
||||
0x00,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x40
|
||||
|
||||
# GFX10: image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x40]
|
||||
# GFX10: image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x40]
|
||||
0x08,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x40
|
||||
|
||||
# GFX10: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40]
|
||||
@ -186,7 +186,7 @@
|
||||
# GFX10: image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0b,0x0f,0x8c,0xf0,0x00,0x00,0x40,0x00,0x02,0x04,0x05,0x06]
|
||||
0x0b,0x0f,0x8c,0xf0,0x00,0x00,0x40,0x00,0x02,0x04,0x05,0x06
|
||||
|
||||
# GFX10: image_sample_c_d_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00]
|
||||
# GFX10: image_sample_c_d_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00]
|
||||
0x01,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00
|
||||
|
||||
# GFX10: image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0d,0x0f,0xac,0xf0,0x00,0x00,0x40,0x00,0x01,0x03,0x05,0x06,0x07,0x00,0x00,0x00]
|
||||
@ -210,7 +210,7 @@
|
||||
# GFX10: image_sample_cd_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0b,0x0f,0xa4,0xf1,0x00,0x00,0x40,0x00,0x02,0x04,0x05,0x06]
|
||||
0x0b,0x0f,0xa4,0xf1,0x00,0x00,0x40,0x00,0x02,0x04,0x05,0x06
|
||||
|
||||
# GFX10: image_sample_c_cd_cl_g16 v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00]
|
||||
# GFX10: image_sample_c_cd_cl_g16 v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x01,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00]
|
||||
0x01,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00
|
||||
|
||||
# GFX10: image_sample_c_cd_cl_g16 v[0:3], [v0, v1, v3, v5, v6, v7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x0d,0x0f,0xac,0xf1,0x00,0x00,0x40,0x00,0x01,0x03,0x05,0x06,0x07,0x00,0x00,0x00]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user