mirror of
https://github.com/RPCS3/llvm-mirror.git
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* TargetData is no longer directly accessable from TM
* s/unsigned int/unsigned/ llvm-svn: 5175
This commit is contained in:
parent
376bdd301b
commit
f34aa0986d
@ -13,6 +13,7 @@
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#include "llvm/CodeGen/InstrForest.h"
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#include "llvm/CodeGen/InstrForest.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iTerminators.h"
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@ -315,7 +316,7 @@ CreateConvertFPToIntInstr(Type::PrimitiveID destTID,
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//
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//
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// Since fdtoi converts to signed integers, any FP value V between MAXINT+1
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// Since fdtoi converts to signed integers, any FP value V between MAXINT+1
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// and MAXUNSIGNED (i.e., 2^31 <= V <= 2^32-1) would be converted incorrectly
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// and MAXUNSIGNED (i.e., 2^31 <= V <= 2^32-1) would be converted incorrectly
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// *only* when converting to an unsigned int. (Unsigned byte, short or long
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// *only* when converting to an unsigned. (Unsigned byte, short or long
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// don't have this problem.)
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// don't have this problem.)
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// For unsigned int, we therefore have to generate the code sequence:
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// For unsigned int, we therefore have to generate the code sequence:
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//
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//
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@ -324,7 +325,7 @@ CreateConvertFPToIntInstr(Type::PrimitiveID destTID,
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// result = result + (unsigned) MAXINT;
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// result = result + (unsigned) MAXINT;
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// }
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// }
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// else
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// else
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// result = (unsigned int) V;
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// result = (unsigned) V;
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//
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//
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static void
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static void
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CreateCodeToConvertFloatToInt(const TargetMachine& target,
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CreateCodeToConvertFloatToInt(const TargetMachine& target,
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@ -338,7 +339,7 @@ CreateCodeToConvertFloatToInt(const TargetMachine& target,
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// depends on the type of FP register to use: single-prec for a 32-bit
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// depends on the type of FP register to use: single-prec for a 32-bit
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// int or smaller; double-prec for a 64-bit int.
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// int or smaller; double-prec for a 64-bit int.
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//
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//
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size_t destSize = target.DataLayout.getTypeSize(destI->getType());
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size_t destSize = target.getTargetData().getTypeSize(destI->getType());
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const Type* destTypeToUse = (destSize > 4)? Type::DoubleTy : Type::FloatTy;
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const Type* destTypeToUse = (destSize > 4)? Type::DoubleTy : Type::FloatTy;
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TmpInstruction* destForCast = new TmpInstruction(destTypeToUse, opVal);
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TmpInstruction* destForCast = new TmpInstruction(destTypeToUse, opVal);
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mcfi.addTemp(destForCast);
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mcfi.addTemp(destForCast);
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@ -522,7 +523,7 @@ CreateShiftInstructions(const TargetMachine& target,
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MachineOpCode shiftOpCode,
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MachineOpCode shiftOpCode,
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Value* argVal1,
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Value* argVal1,
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Value* optArgVal2, /* Use optArgVal2 if not NULL */
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Value* optArgVal2, /* Use optArgVal2 if not NULL */
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unsigned int optShiftNum, /* else use optShiftNum */
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unsigned optShiftNum, /* else use optShiftNum */
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Instruction* destVal,
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Instruction* destVal,
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vector<MachineInstr*>& mvec,
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vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)
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MachineCodeForInstruction& mcfi)
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@ -536,9 +537,9 @@ CreateShiftInstructions(const TargetMachine& target,
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// of dest, so we need to put the result of the SLL into a temporary.
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// of dest, so we need to put the result of the SLL into a temporary.
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//
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//
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Value* shiftDest = destVal;
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Value* shiftDest = destVal;
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unsigned opSize = target.DataLayout.getTypeSize(argVal1->getType());
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unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
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if ((shiftOpCode == SLL || shiftOpCode == SLLX)
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if ((shiftOpCode == SLL || shiftOpCode == SLLX)
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&& opSize < target.DataLayout.getIntegerRegize())
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&& opSize < target.getTargetData().getIntegerRegize())
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{ // put SLL result into a temporary
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{ // put SLL result into a temporary
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shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
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shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
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mcfi.addTemp(shiftDest);
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mcfi.addTemp(shiftDest);
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@ -563,15 +564,15 @@ CreateShiftInstructions(const TargetMachine& target,
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// create a cheaper instruction.
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// create a cheaper instruction.
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// This returns the approximate cost of the instructions generated,
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// This returns the approximate cost of the instructions generated,
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// which is used to pick the cheapest when both operands are constant.
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// which is used to pick the cheapest when both operands are constant.
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static inline unsigned int
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static inline unsigned
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CreateMulConstInstruction(const TargetMachine &target, Function* F,
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CreateMulConstInstruction(const TargetMachine &target, Function* F,
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Value* lval, Value* rval, Instruction* destVal,
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Value* lval, Value* rval, Instruction* destVal,
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vector<MachineInstr*>& mvec,
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vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi)
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MachineCodeForInstruction& mcfi)
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{
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{
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/* Use max. multiply cost, viz., cost of MULX */
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/* Use max. multiply cost, viz., cost of MULX */
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unsigned int cost = target.getInstrInfo().minLatency(MULX);
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unsigned cost = target.getInstrInfo().minLatency(MULX);
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unsigned int firstNewInstr = mvec.size();
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unsigned firstNewInstr = mvec.size();
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Value* constOp = rval;
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Value* constOp = rval;
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if (! isa<Constant>(constOp))
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if (! isa<Constant>(constOp))
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@ -612,7 +613,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
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}
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}
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else if (isPowerOf2(C, pow))
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else if (isPowerOf2(C, pow))
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{
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{
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unsigned int opSize = target.DataLayout.getTypeSize(resultType);
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unsigned opSize = target.getTargetData().getTypeSize(resultType);
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MachineOpCode opCode = (opSize <= 32)? SLL : SLLX;
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MachineOpCode opCode = (opSize <= 32)? SLL : SLLX;
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CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
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CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
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destVal, mvec, mcfi);
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destVal, mvec, mcfi);
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@ -644,7 +645,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
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if (firstNewInstr < mvec.size())
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if (firstNewInstr < mvec.size())
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{
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{
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cost = 0;
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cost = 0;
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for (unsigned int i=firstNewInstr; i < mvec.size(); ++i)
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for (unsigned i=firstNewInstr; i < mvec.size(); ++i)
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cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode());
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cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode());
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}
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}
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@ -687,7 +688,7 @@ CreateMulInstruction(const TargetMachine &target, Function* F,
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MachineCodeForInstruction& mcfi,
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MachineCodeForInstruction& mcfi,
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MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
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MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
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{
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{
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unsigned int L = mvec.size();
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unsigned L = mvec.size();
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CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi);
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CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi);
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if (mvec.size() == L)
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if (mvec.size() == L)
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{ // no instructions were added so create MUL reg, reg, reg.
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{ // no instructions were added so create MUL reg, reg, reg.
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@ -829,7 +830,7 @@ CreateDivConstInstruction(TargetMachine &target,
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static void
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static void
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CreateCodeForVariableSizeAlloca(const TargetMachine& target,
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CreateCodeForVariableSizeAlloca(const TargetMachine& target,
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Instruction* result,
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Instruction* result,
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unsigned int tsize,
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unsigned tsize,
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Value* numElementsVal,
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Value* numElementsVal,
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vector<MachineInstr*>& getMvec)
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vector<MachineInstr*>& getMvec)
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{
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{
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@ -895,7 +896,8 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
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// Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
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// Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
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M = new MachineInstr(ADD);
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M = new MachineInstr(ADD);
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M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
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M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
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dynamicAreaOffset);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
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getMvec.push_back(M);
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getMvec.push_back(M);
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}
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}
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@ -904,8 +906,8 @@ CreateCodeForVariableSizeAlloca(const TargetMachine& target,
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static void
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static void
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CreateCodeForFixedSizeAlloca(const TargetMachine& target,
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CreateCodeForFixedSizeAlloca(const TargetMachine& target,
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Instruction* result,
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Instruction* result,
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unsigned int tsize,
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unsigned tsize,
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unsigned int numElements,
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unsigned numElements,
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vector<MachineInstr*>& getMvec)
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vector<MachineInstr*>& getMvec)
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{
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{
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assert(tsize > 0 && "Illegal (zero) type size for alloca");
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assert(tsize > 0 && "Illegal (zero) type size for alloca");
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@ -918,20 +920,19 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target,
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// load/stores (check LDX because all load/stores have the same-size immediate
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// load/stores (check LDX because all load/stores have the same-size immediate
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// field). If not, put the variable in the dynamically sized area of the
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// field). If not, put the variable in the dynamically sized area of the
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// frame.
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// frame.
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unsigned int paddedSizeIgnored;
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unsigned paddedSizeIgnored;
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int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result,
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int offsetFromFP = mcInfo.getInfo()->computeOffsetforLocalVar(result,
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paddedSizeIgnored,
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paddedSizeIgnored,
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tsize * numElements);
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tsize * numElements);
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if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP))
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if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP)) {
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{
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CreateCodeForVariableSizeAlloca(target, result, tsize,
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CreateCodeForVariableSizeAlloca(target, result, tsize,
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ConstantSInt::get(Type::IntTy,numElements),
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ConstantSInt::get(Type::IntTy,numElements),
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getMvec);
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getMvec);
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return;
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return;
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}
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}
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// else offset fits in immediate field so go ahead and allocate it.
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// else offset fits in immediate field so go ahead and allocate it.
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offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements);
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offsetFromFP = mcInfo.getInfo()->allocateLocalVar(result, tsize *numElements);
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// Create a temporary Value to hold the constant offset.
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// Create a temporary Value to hold the constant offset.
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// This is needed because it may not fit in the immediate field.
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// This is needed because it may not fit in the immediate field.
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@ -995,7 +996,7 @@ SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
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{
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{
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// Compute the offset value using the index vector. Create a
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// Compute the offset value using the index vector. Create a
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// virtual reg. for it since it may not fit in the immed field.
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// virtual reg. for it since it may not fit in the immed field.
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uint64_t offset = target.DataLayout.getIndexedOffset(ptrType,idxVec);
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uint64_t offset = target.getTargetData().getIndexedOffset(ptrType,idxVec);
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valueForRegOffset = ConstantSInt::get(Type::LongTy, offset);
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valueForRegOffset = ConstantSInt::get(Type::LongTy, offset);
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}
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}
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else
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else
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@ -1025,7 +1026,7 @@ SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
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: ptrType);
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: ptrType);
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const Type* eltType = cast<SequentialType>(vecType)->getElementType();
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const Type* eltType = cast<SequentialType>(vecType)->getElementType();
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ConstantUInt* eltSizeVal = ConstantUInt::get(Type::ULongTy,
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ConstantUInt* eltSizeVal = ConstantUInt::get(Type::ULongTy,
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target.DataLayout.getTypeSize(eltType));
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target.getTargetData().getTypeSize(eltType));
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// CreateMulInstruction() folds constants intelligently enough.
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// CreateMulInstruction() folds constants intelligently enough.
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CreateMulInstruction(target, memInst->getParent()->getParent(),
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CreateMulInstruction(target, memInst->getParent()->getParent(),
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@ -1222,9 +1223,9 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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bool maskUnsignedResult = false;
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bool maskUnsignedResult = false;
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int nextRule;
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int nextRule;
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int forwardOperandNum = -1;
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int forwardOperandNum = -1;
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unsigned int allocaSize = 0;
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unsigned allocaSize = 0;
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MachineInstr* M, *M2;
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MachineInstr* M, *M2;
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unsigned int L;
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unsigned L;
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mvec.clear();
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mvec.clear();
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@ -1498,8 +1499,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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const Type* opType = opVal->getType();
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const Type* opType = opVal->getType();
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if (opType->isIntegral() || isa<PointerType>(opType))
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if (opType->isIntegral() || isa<PointerType>(opType))
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{
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{
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unsigned opSize = target.DataLayout.getTypeSize(opType);
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unsigned opSize = target.getTargetData().getTypeSize(opType);
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unsigned destSize = target.DataLayout.getTypeSize(destI->getType());
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unsigned destSize = target.getTargetData().getTypeSize(destI->getType());
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if (opSize >= destSize)
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if (opSize >= destSize)
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{ // Operand is same size as or larger than dest:
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{ // Operand is same size as or larger than dest:
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// zero- or sign-extend, according to the signeddness of
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// zero- or sign-extend, according to the signeddness of
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@ -1592,7 +1593,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// double-prec for a 64-bit int.
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// double-prec for a 64-bit int.
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//
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//
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uint64_t srcSize =
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uint64_t srcSize =
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target.DataLayout.getTypeSize(leftVal->getType());
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target.getTargetData().getTypeSize(leftVal->getType());
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Type* tmpTypeToUse =
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Type* tmpTypeToUse =
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(srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
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(srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
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srcForCast = new TmpInstruction(tmpTypeToUse, dest);
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srcForCast = new TmpInstruction(tmpTypeToUse, dest);
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@ -1703,7 +1704,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 36: // reg: Div(reg, reg)
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case 36: // reg: Div(reg, reg)
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maskUnsignedResult = true;
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maskUnsignedResult = true;
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mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot)));
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mvec.push_back(new MachineInstr(ChooseDivInstruction(target,
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subtreeRoot)));
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Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
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Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
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break;
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break;
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@ -1947,8 +1949,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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{ // add %fp, offsetFromFP -> result
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{ // add %fp, offsetFromFP -> result
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AllocationInst* instr =
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AllocationInst* instr =
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cast<AllocationInst>(subtreeRoot->getInstruction());
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cast<AllocationInst>(subtreeRoot->getInstruction());
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unsigned int tsize =
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unsigned tsize =
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target.DataLayout.getTypeSize(instr->getAllocatedType());
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target.getTargetData().getTypeSize(instr->getAllocatedType());
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assert(tsize != 0);
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assert(tsize != 0);
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CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
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CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
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break;
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break;
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@ -1963,14 +1965,14 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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const Type* eltType = instr->getAllocatedType();
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const Type* eltType = instr->getAllocatedType();
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// If #elements is constant, use simpler code for fixed-size allocas
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// If #elements is constant, use simpler code for fixed-size allocas
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int tsize = (int) target.DataLayout.getTypeSize(eltType);
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int tsize = (int) target.getTargetData().getTypeSize(eltType);
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Value* numElementsVal = NULL;
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Value* numElementsVal = NULL;
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bool isArray = instr->isArrayAllocation();
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bool isArray = instr->isArrayAllocation();
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if (!isArray ||
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if (!isArray ||
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isa<Constant>(numElementsVal = instr->getArraySize()))
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isa<Constant>(numElementsVal = instr->getArraySize()))
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{ // total size is constant: generate code for fixed-size alloca
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{ // total size is constant: generate code for fixed-size alloca
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unsigned int numElements = isArray?
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unsigned numElements = isArray?
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cast<ConstantUInt>(numElementsVal)->getValue() : 1;
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cast<ConstantUInt>(numElementsVal)->getValue() : 1;
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CreateCodeForFixedSizeAlloca(target, instr, tsize,
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CreateCodeForFixedSizeAlloca(target, instr, tsize,
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numElements, mvec);
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numElements, mvec);
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@ -2157,7 +2159,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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Instruction* dest = subtreeRoot->getInstruction();
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Instruction* dest = subtreeRoot->getInstruction();
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if (dest->getType()->isUnsigned())
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if (dest->getType()->isUnsigned())
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{
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{
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unsigned destSize = target.DataLayout.getTypeSize(dest->getType());
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unsigned destSize=target.getTargetData().getTypeSize(dest->getType());
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if (destSize <= 4)
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if (destSize <= 4)
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{ // Mask high bits. Use a TmpInstruction to represent the
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{ // Mask high bits. Use a TmpInstruction to represent the
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// intermediate result before masking. Since those instructions
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// intermediate result before masking. Since those instructions
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@ -2173,7 +2175,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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M = Create3OperandInstr_UImmed(SRL, tmpI, 8*(4-destSize), dest);
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M = Create3OperandInstr_UImmed(SRL, tmpI, 8*(4-destSize), dest);
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mvec.push_back(M);
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mvec.push_back(M);
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}
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}
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else if (destSize < target.DataLayout.getIntegerRegize())
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else if (destSize < target.getTargetData().getIntegerRegize())
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assert(0 && "Unsupported type size: 32 < size < 64 bits");
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assert(0 && "Unsupported type size: 32 < size < 64 bits");
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}
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}
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}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user