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Revert r265450 "[X86] Reuse EFLAGS and form LOCKed ops when only user is SETCC."
It caused ASan 32-bit tests to hang (PR27245). llvm-svn: 265559
This commit is contained in:
Hans Wennborg
parent
f8a916174c
commit
f357d442d6
@ -26135,56 +26135,6 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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/// Combine:
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/// (brcond/cmov/setcc .., (cmp (atomic_load_op ..), 0), cc)
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/// to:
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/// (brcond/cmov/setcc .., (LOCKed op ..), cc)
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/// i.e., reusing the EFLAGS produced by the LOCKed instruction.
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/// Note that this is only legal for some op/cc combinations.
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static SDValue combineSetCCAtomicArith(SDValue Cmp, X86::CondCode CC,
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SelectionDAG &DAG) {
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// This combine only operates on CMP-like nodes.
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if (!(Cmp.getOpcode() == X86ISD::CMP ||
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(Cmp.getOpcode() == X86ISD::SUB && !Cmp->hasAnyUseOfValue(0))))
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return SDValue();
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SDValue LHS = Cmp.getOperand(0);
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SDValue RHS = Cmp.getOperand(1);
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if (!LHS.hasOneUse())
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return SDValue();
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// FIXME: We can do this for XOR/OR/AND as well, but only if they survive
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// AtomicExpand. Currently, we choose to expand them to cmpxchg if they
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// have any users. Could we relax that to ignore (icmp x,0) users?
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switch (LHS->getOpcode()) {
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case ISD::ATOMIC_LOAD_ADD:
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case ISD::ATOMIC_LOAD_SUB:
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break;
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default:
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return SDValue();
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}
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auto *C = dyn_cast<ConstantSDNode>(RHS);
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if (!C || C->getZExtValue() != 0)
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return SDValue();
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// Don't do this for all condition codes, as OF/CF are cleared by (CMP x,0)
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// but might be set by arithmetic. Furthermore, we might later select INC/DEC,
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// which don't modify CF (though CCs using CF should have been optimized out).
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// SF/ZF are safe as they are set the same way.
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// Note that in theory, the transformation is also valid for P/NP.
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if (CC != X86::COND_E && CC != X86::COND_NE && CC != X86::COND_S &&
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CC != X86::COND_NS)
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return SDValue();
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SDValue LockOp = lowerAtomicArithWithLOCK(LHS, DAG);
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DAG.ReplaceAllUsesOfValueWith(LHS.getValue(0),
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DAG.getUNDEF(LHS.getValueType()));
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DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LockOp.getValue(1));
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return LockOp;
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}
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// Check whether a boolean test is testing a boolean value generated by
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// X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
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// code.
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@ -26356,16 +26306,6 @@ static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
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return true;
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}
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/// Optimize an EFLAGS definition used according to the condition code \p CC
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/// into a simpler EFLAGS value, potentially returning a new \p CC and replacing
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/// uses of chain values.
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static SDValue combineSetCCEFLAGS(SDValue EFLAGS, X86::CondCode &CC,
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SelectionDAG &DAG) {
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if (SDValue R = checkBoolTestSetCCCombine(EFLAGS, CC))
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return R;
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return combineSetCCAtomicArith(EFLAGS, CC, DAG);
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}
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/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
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static SDValue combineCMov(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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@ -26392,14 +26332,15 @@ static SDValue combineCMov(SDNode *N, SelectionDAG &DAG,
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}
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}
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// Try to simplify the EFLAGS and condition code operands.
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// We can't always do this as FCMOV only supports a subset of X86 cond.
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if (SDValue Flags = combineSetCCEFLAGS(Cond, CC, DAG)) {
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if (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC)) {
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SDValue Ops[] = {FalseOp, TrueOp, DAG.getConstant(CC, DL, MVT::i8),
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Flags};
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return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
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}
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SDValue Flags;
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Flags = checkBoolTestSetCCCombine(Cond, CC);
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if (Flags.getNode() &&
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// Extra check as FCMOV only supports a subset of X86 cond.
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(FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
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SDValue Ops[] = { FalseOp, TrueOp,
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DAG.getConstant(CC, DL, MVT::i8), Flags };
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return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
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}
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// If this is a select between two integer constants, try to do some
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@ -29325,8 +29266,7 @@ static SDValue combineX86SetCC(SDNode *N, SelectionDAG &DAG,
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if (CC == X86::COND_B)
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return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
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// Try to simplify the EFLAGS and condition code operands.
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if (SDValue Flags = combineSetCCEFLAGS(EFLAGS, CC, DAG)) {
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if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
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SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
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return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
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}
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@ -29339,16 +29279,15 @@ static SDValue combineBrCond(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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SDLoc DL(N);
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SDValue Chain = N->getOperand(0);
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SDValue Dest = N->getOperand(1);
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SDValue EFLAGS = N->getOperand(3);
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X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
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// Try to simplify the EFLAGS and condition code operands.
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// Make sure to not keep references to operands, as combineSetCCEFLAGS can
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// RAUW them under us.
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if (SDValue Flags = combineSetCCEFLAGS(EFLAGS, CC, DAG)) {
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if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
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SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
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return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), N->getOperand(0),
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N->getOperand(1), Cond, Flags);
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return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
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Flags);
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}
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return SDValue();
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@ -4,7 +4,9 @@
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define i8 @test_add_1_setcc_ne(i64* %p) #0 {
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; CHECK-LABEL: test_add_1_setcc_ne:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lock incq (%rdi)
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: testq %rax, %rax
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: retq
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entry:
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@ -17,7 +19,9 @@ entry:
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define i8 @test_sub_1_setcc_eq(i64* %p) #0 {
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; CHECK-LABEL: test_sub_1_setcc_eq:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lock decq (%rdi)
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; CHECK-NEXT: movq $-1, %rax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: testq %rax, %rax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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entry:
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@ -45,7 +49,9 @@ entry:
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define i8 @test_sub_10_setcc_sge(i64* %p) #0 {
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; CHECK-LABEL: test_sub_10_setcc_sge:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lock addq $-10, (%rdi)
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; CHECK-NEXT: movq $-10, %rax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: testq %rax, %rax
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; CHECK-NEXT: setns %al
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; CHECK-NEXT: retq
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entry:
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@ -60,7 +66,9 @@ entry:
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define i32 @test_add_10_brcond_sge(i64* %p, i32 %a0, i32 %a1) #0 {
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; CHECK-LABEL: test_add_10_brcond_sge:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lock addq $10, (%rdi)
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; CHECK-NEXT: movl $10, %eax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: testq %rax, %rax
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; CHECK-NEXT: js .LBB4_2
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; CHECK-NEXT: # BB#1: # %t
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; CHECK-NEXT: movl %esi, %eax
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@ -81,7 +89,9 @@ f:
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define i32 @test_sub_1_cmov_slt(i64* %p, i32 %a0, i32 %a1) #0 {
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; CHECK-LABEL: test_sub_1_cmov_slt:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lock decq (%rdi)
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; CHECK-NEXT: movq $-1, %rax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: testq %rax, %rax
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; CHECK-NEXT: cmovnsl %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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