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[Hexagon] Misc fixes to r255807
llvm-svn: 255811
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@ -462,13 +462,13 @@ static const MachineOperand &getPostIncrementOperand(const MachineInstr *MI,
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return MO;
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return MO;
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#else
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#else
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if (MI->mayLoad()) {
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if (MI->mayLoad()) {
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MachineOperand &Op1 = MI->getOperand(1);
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const MachineOperand &Op1 = MI->getOperand(1);
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// The 2nd operand is always the post increment operand in load.
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// The 2nd operand is always the post increment operand in load.
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assert(Op1.isReg() && "Post increment operand has be to a register.");
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assert(Op1.isReg() && "Post increment operand has be to a register.");
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return Op1;
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return Op1;
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}
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}
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if (MI->getDesc().mayStore()) {
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if (MI->getDesc().mayStore()) {
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MachineOperand &Op0 = MI->getOperand(0);
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const MachineOperand &Op0 = MI->getOperand(0);
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// The 1st operand is always the post increment operand in store.
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// The 1st operand is always the post increment operand in store.
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assert(Op0.isReg() && "Post increment operand has be to a register.");
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assert(Op0.isReg() && "Post increment operand has be to a register.");
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return Op0;
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return Op0;
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@ -1162,16 +1162,11 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
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MachineInstr *NextMI = NextMII;
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MachineInstr *NextMI = NextMII;
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bool secondRegMatch = false;
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bool secondRegMatch = false;
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bool maintainNewValueJump = false;
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const MachineOperand &NOp0 = NextMI->getOperand(0);
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const MachineOperand &NOp0 = NextMI->getOperand(0);
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const MachineOperand &NOp1 = NextMI->getOperand(1);
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const MachineOperand &NOp1 = NextMI->getOperand(1);
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if (NOp1.isReg() && I->getOperand(0).getReg() == NOp1.getReg()) {
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if (NOp1.isReg() && I->getOperand(0).getReg() == NOp1.getReg())
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secondRegMatch = true;
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secondRegMatch = true;
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maintainNewValueJump = true;
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} else if (I->getOperand(0).getReg() == NOp0.getReg()) {
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maintainNewValueJump = true;
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}
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for (auto I : CurrentPacketMIs) {
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for (auto I : CurrentPacketMIs) {
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SUnit *PacketSU = MIToSUnit.find(I)->second;
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SUnit *PacketSU = MIToSUnit.find(I)->second;
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