mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 11:33:24 +02:00
This patch is in preparation for a substantial refactoring of the
code. To make the diffs easier to read, clang-format everything first. No functionality changed. Patch by Alina Sbirlea! http://reviews.llvm.org/D20926 llvm-svn: 271595
This commit is contained in:
Eric Christopher
parent
1c98eb67fa
commit
f3784f237a
@ -33,9 +33,9 @@
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#include <intrin.h>
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#endif
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#if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
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#include <mach/host_info.h>
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#include <mach/mach.h>
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#include <mach/mach_host.h>
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#include <mach/host_info.h>
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#include <mach/machine.h>
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#endif
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@ -69,40 +69,36 @@ static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
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}
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#endif
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(i386) || defined(__i386__) || defined(__x86__) || \
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defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \
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defined(_M_X64)
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/// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
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/// the
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/// specified arguments. If we can't run cpuid on the host, return true.
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static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
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unsigned *rECX, unsigned *rEDX) {
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#if defined(__GNUC__) || defined(__clang__)
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#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
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: "a"(value));
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return false;
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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asm("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
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: "a"(value));
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return false;
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// pedantic #else returns to appease -Wunreachable-code (so we don't generate
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// postprocessed code that looks like "return true; return false;")
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#else
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return true;
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#endif
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#else
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return true;
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#endif
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#elif defined(_MSC_VER)
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// The MSVC intrinsic is portable across x86 and x64.
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int registers[4];
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@ -117,50 +113,43 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
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#endif
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}
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/// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
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/// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
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/// the
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/// 4 values in the specified arguments. If we can't run cpuid on the host,
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/// return true.
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static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
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unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
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unsigned *rEDX) {
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#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(__GNUC__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value),
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"c" (subleaf));
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return false;
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#elif defined(_MSC_VER)
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int registers[4];
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__cpuidex(registers, value, subleaf);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#else
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return true;
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#endif
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#if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
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#if defined(__GNUC__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
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: "a"(value), "c"(subleaf));
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return false;
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#elif defined(_MSC_VER)
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int registers[4];
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__cpuidex(registers, value, subleaf);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#else
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return true;
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#endif
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value),
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"c" (subleaf));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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#if defined(__GNUC__)
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asm("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
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: "a"(value), "c"(subleaf));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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mov ecx,subleaf
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cpuid
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@ -172,11 +161,11 @@ static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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#else
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return true;
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#endif
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}
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return false;
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#else
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return true;
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#endif
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#else
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return true;
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#endif
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@ -187,7 +176,7 @@ static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) {
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// Check xgetbv; this uses a .byte sequence instead of the instruction
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// directly because older assemblers do not include support for xgetbv and
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// there is no easy way to conditionally compile based on the assembler used.
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__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (*rEAX), "=d" (*rEDX) : "c" (0));
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__asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
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return false;
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#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
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unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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@ -202,11 +191,11 @@ static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) {
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static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
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unsigned &Model) {
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Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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if (Family == 6 || Family == 0xf) {
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if (Family == 0xf)
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// Examine extended family ID if family ID is F.
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Family += (EAX >> 20) & 0xff; // Bits 20 - 27
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Family += (EAX >> 20) & 0xff; // Bits 20 - 27
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// Examine extended model ID if family ID is 6 or F.
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Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
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}
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@ -217,22 +206,22 @@ StringRef sys::getHostCPUName() {
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if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
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return "generic";
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unsigned Family = 0;
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unsigned Model = 0;
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unsigned Model = 0;
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DetectX86FamilyModel(EAX, Family, Model);
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union {
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unsigned u[3];
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char c[12];
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char c[12];
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} text;
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unsigned MaxLeaf;
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GetX86CpuIDAndInfo(0, &MaxLeaf, text.u+0, text.u+2, text.u+1);
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GetX86CpuIDAndInfo(0, &MaxLeaf, text.u + 0, text.u + 2, text.u + 1);
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bool HasMMX = (EDX >> 23) & 1;
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bool HasSSE = (EDX >> 25) & 1;
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bool HasSSE2 = (EDX >> 26) & 1;
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bool HasSSE3 = (ECX >> 0) & 1;
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bool HasSSSE3 = (ECX >> 9) & 1;
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bool HasMMX = (EDX >> 23) & 1;
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bool HasSSE = (EDX >> 25) & 1;
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bool HasSSE2 = (EDX >> 26) & 1;
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bool HasSSE3 = (ECX >> 0) & 1;
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bool HasSSSE3 = (ECX >> 9) & 1;
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bool HasSSE41 = (ECX >> 19) & 1;
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bool HasSSE42 = (ECX >> 20) & 1;
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bool HasMOVBE = (ECX >> 22) & 1;
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@ -243,8 +232,8 @@ StringRef sys::getHostCPUName() {
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bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) &&
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((EAX & 0x6) == 0x6);
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bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
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bool HasLeaf7 = MaxLeaf >= 0x7 &&
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!GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
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bool HasLeaf7 =
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MaxLeaf >= 0x7 && !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
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bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
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bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
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bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
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@ -268,25 +257,27 @@ StringRef sys::getHostCPUName() {
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case 5: // IntelSX2 processors
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case 7: // Write-Back Enhanced IntelDX2 processors
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case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
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default: return "i486";
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default:
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return "i486";
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}
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case 5:
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switch (Model) {
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case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
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// Pentium processors (60, 66)
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case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
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// 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
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// 150, 166, 200)
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case 3: // Pentium OverDrive processors for Intel486 processor-based
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// systems
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case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
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// Pentium processors (60, 66)
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case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
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// 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
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// 150, 166, 200)
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case 3: // Pentium OverDrive processors for Intel486 processor-based
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// systems
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return "pentium";
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case 4: // Pentium OverDrive processor with MMX technology for Pentium
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// processor (75, 90, 100, 120, 133), Pentium processor with
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// MMX technology (166, 200)
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case 4: // Pentium OverDrive processor with MMX technology for Pentium
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// processor (75, 90, 100, 120, 133), Pentium processor with
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// MMX technology (166, 200)
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return "pentium-mmx";
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default: return "pentium";
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default:
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return "pentium";
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}
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case 6:
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switch (Model) {
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@ -308,31 +299,33 @@ StringRef sys::getHostCPUName() {
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case 0x0b: // Pentium III processor, model 0Bh
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return "pentium3";
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case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
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case 0x09: // Intel Pentium M processor, Intel Celeron M processor model
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// 09.
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case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
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// 0Dh. All processors are manufactured using the 90 nm process.
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// 0Dh. All processors are manufactured using the 90 nm process.
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case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
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// Integrated Processor with Intel QuickAssist Technology
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return "pentium-m";
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case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
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// 0Eh. All processors are manufactured using the 65 nm process.
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// 0Eh. All processors are manufactured using the 65 nm process.
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return "yonah";
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case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
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// processor, Intel Core 2 Quad processor, Intel Core 2 Quad
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// mobile processor, Intel Core 2 Extreme processor, Intel
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// Pentium Dual-Core processor, Intel Xeon processor, model
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// 0Fh. All processors are manufactured using the 65 nm process.
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// 0Fh. All processors are manufactured using the 65 nm process.
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case 0x16: // Intel Celeron processor model 16h. All processors are
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// manufactured using the 65 nm process
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return "core2";
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case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
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// 17h. All processors are manufactured using the 45 nm process.
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//
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// 45nm: Penryn , Wolfdale, Yorkfield (XE)
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case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
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// 17h. All processors are manufactured using the 45 nm process.
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//
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// 45nm: Penryn , Wolfdale, Yorkfield (XE)
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case 0x1d: // Intel Xeon processor MP. All processors are manufactured
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// using
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// the 45 nm process.
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return "penryn";
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@ -423,28 +416,28 @@ StringRef sys::getHostCPUName() {
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}
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case 15: {
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switch (Model) {
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case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
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// model 00h and manufactured using the 0.18 micron process.
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case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
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// processor MP, and Intel Celeron processor. All processors are
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// model 01h and manufactured using the 0.18 micron process.
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case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
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// Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
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// processor, and Mobile Intel Celeron processor. All processors
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// are model 02h and manufactured using the 0.13 micron process.
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case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
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// model 00h and manufactured using the 0.18 micron process.
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case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
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// processor MP, and Intel Celeron processor. All processors are
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// model 01h and manufactured using the 0.18 micron process.
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case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
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// Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
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// processor, and Mobile Intel Celeron processor. All processors
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// are model 02h and manufactured using the 0.13 micron process.
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return (Em64T) ? "x86-64" : "pentium4";
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case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
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// processor. All processors are model 03h and manufactured using
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// the 90 nm process.
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case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
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// Pentium D processor, Intel Xeon processor, Intel Xeon
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// processor MP, Intel Celeron D processor. All processors are
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// model 04h and manufactured using the 90 nm process.
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case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
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// Extreme Edition, Intel Xeon processor, Intel Xeon processor
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// MP, Intel Celeron D processor. All processors are model 06h
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// and manufactured using the 65 nm process.
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case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
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// processor. All processors are model 03h and manufactured using
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// the 90 nm process.
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case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
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// Pentium D processor, Intel Xeon processor, Intel Xeon
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// processor MP, Intel Celeron D processor. All processors are
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// model 04h and manufactured using the 90 nm process.
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case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
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// Extreme Edition, Intel Xeon processor, Intel Xeon processor
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// MP, Intel Celeron D processor. All processors are model 06h
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// and manufactured using the 65 nm process.
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return (Em64T) ? "nocona" : "prescott";
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default:
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@ -460,53 +453,65 @@ StringRef sys::getHostCPUName() {
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// appears to be no way to generate the wide variety of AMD-specific targets
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// from the information returned from CPUID.
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switch (Family) {
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 6:
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case 7: return "k6";
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case 8: return "k6-2";
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case 9:
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case 13: return "k6-3";
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case 10: return "geode";
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default: return "pentium";
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}
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case 4:
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return "i486";
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||||
case 5:
|
||||
switch (Model) {
|
||||
case 6:
|
||||
switch (Model) {
|
||||
case 4: return "athlon-tbird";
|
||||
case 6:
|
||||
case 7:
|
||||
case 8: return "athlon-mp";
|
||||
case 10: return "athlon-xp";
|
||||
default: return "athlon";
|
||||
}
|
||||
case 15:
|
||||
if (HasSSE3)
|
||||
return "k8-sse3";
|
||||
switch (Model) {
|
||||
case 1: return "opteron";
|
||||
case 5: return "athlon-fx"; // also opteron
|
||||
default: return "athlon64";
|
||||
}
|
||||
case 16:
|
||||
return "amdfam10";
|
||||
case 20:
|
||||
case 7:
|
||||
return "k6";
|
||||
case 8:
|
||||
return "k6-2";
|
||||
case 9:
|
||||
case 13:
|
||||
return "k6-3";
|
||||
case 10:
|
||||
return "geode";
|
||||
default:
|
||||
return "pentium";
|
||||
}
|
||||
case 6:
|
||||
switch (Model) {
|
||||
case 4:
|
||||
return "athlon-tbird";
|
||||
case 6:
|
||||
case 7:
|
||||
case 8:
|
||||
return "athlon-mp";
|
||||
case 10:
|
||||
return "athlon-xp";
|
||||
default:
|
||||
return "athlon";
|
||||
}
|
||||
case 15:
|
||||
if (HasSSE3)
|
||||
return "k8-sse3";
|
||||
switch (Model) {
|
||||
case 1:
|
||||
return "opteron";
|
||||
case 5:
|
||||
return "athlon-fx"; // also opteron
|
||||
default:
|
||||
return "athlon64";
|
||||
}
|
||||
case 16:
|
||||
return "amdfam10";
|
||||
case 20:
|
||||
return "btver1";
|
||||
case 21:
|
||||
if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
|
||||
return "btver1";
|
||||
case 21:
|
||||
if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
|
||||
return "btver1";
|
||||
if (Model >= 0x50)
|
||||
return "bdver4"; // 50h-6Fh: Excavator
|
||||
if (Model >= 0x30)
|
||||
return "bdver3"; // 30h-3Fh: Steamroller
|
||||
if (Model >= 0x10 || HasTBM)
|
||||
return "bdver2"; // 10h-1Fh: Piledriver
|
||||
return "bdver1"; // 00h-0Fh: Bulldozer
|
||||
case 22:
|
||||
if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
|
||||
return "btver1";
|
||||
return "btver2";
|
||||
if (Model >= 0x50)
|
||||
return "bdver4"; // 50h-6Fh: Excavator
|
||||
if (Model >= 0x30)
|
||||
return "bdver3"; // 30h-3Fh: Steamroller
|
||||
if (Model >= 0x10 || HasTBM)
|
||||
return "bdver2"; // 10h-1Fh: Piledriver
|
||||
return "bdver1"; // 00h-0Fh: Bulldozer
|
||||
case 22:
|
||||
if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
|
||||
return "btver1";
|
||||
return "btver2";
|
||||
default:
|
||||
return "generic";
|
||||
}
|
||||
@ -519,27 +524,40 @@ StringRef sys::getHostCPUName() {
|
||||
mach_msg_type_number_t infoCount;
|
||||
|
||||
infoCount = HOST_BASIC_INFO_COUNT;
|
||||
host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
|
||||
host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
|
||||
&infoCount);
|
||||
|
||||
if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
|
||||
|
||||
switch(hostInfo.cpu_subtype) {
|
||||
case CPU_SUBTYPE_POWERPC_601: return "601";
|
||||
case CPU_SUBTYPE_POWERPC_602: return "602";
|
||||
case CPU_SUBTYPE_POWERPC_603: return "603";
|
||||
case CPU_SUBTYPE_POWERPC_603e: return "603e";
|
||||
case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
|
||||
case CPU_SUBTYPE_POWERPC_604: return "604";
|
||||
case CPU_SUBTYPE_POWERPC_604e: return "604e";
|
||||
case CPU_SUBTYPE_POWERPC_620: return "620";
|
||||
case CPU_SUBTYPE_POWERPC_750: return "750";
|
||||
case CPU_SUBTYPE_POWERPC_7400: return "7400";
|
||||
case CPU_SUBTYPE_POWERPC_7450: return "7450";
|
||||
case CPU_SUBTYPE_POWERPC_970: return "970";
|
||||
default: ;
|
||||
if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
|
||||
return "generic";
|
||||
|
||||
switch (hostInfo.cpu_subtype) {
|
||||
case CPU_SUBTYPE_POWERPC_601:
|
||||
return "601";
|
||||
case CPU_SUBTYPE_POWERPC_602:
|
||||
return "602";
|
||||
case CPU_SUBTYPE_POWERPC_603:
|
||||
return "603";
|
||||
case CPU_SUBTYPE_POWERPC_603e:
|
||||
return "603e";
|
||||
case CPU_SUBTYPE_POWERPC_603ev:
|
||||
return "603ev";
|
||||
case CPU_SUBTYPE_POWERPC_604:
|
||||
return "604";
|
||||
case CPU_SUBTYPE_POWERPC_604e:
|
||||
return "604e";
|
||||
case CPU_SUBTYPE_POWERPC_620:
|
||||
return "620";
|
||||
case CPU_SUBTYPE_POWERPC_750:
|
||||
return "750";
|
||||
case CPU_SUBTYPE_POWERPC_7400:
|
||||
return "7400";
|
||||
case CPU_SUBTYPE_POWERPC_7450:
|
||||
return "7450";
|
||||
case CPU_SUBTYPE_POWERPC_970:
|
||||
return "970";
|
||||
default:;
|
||||
}
|
||||
|
||||
|
||||
return "generic";
|
||||
}
|
||||
#elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
|
||||
@ -578,12 +596,12 @@ StringRef sys::getHostCPUName() {
|
||||
++CIP;
|
||||
while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
|
||||
++CIP;
|
||||
|
||||
|
||||
if (CIP < CPUInfoEnd && *CIP == ':') {
|
||||
++CIP;
|
||||
while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
|
||||
++CIP;
|
||||
|
||||
|
||||
if (CIP < CPUInfoEnd) {
|
||||
CPUStart = CIP;
|
||||
while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
|
||||
@ -605,25 +623,25 @@ StringRef sys::getHostCPUName() {
|
||||
return generic;
|
||||
|
||||
return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
|
||||
.Case("604e", "604e")
|
||||
.Case("604", "604")
|
||||
.Case("7400", "7400")
|
||||
.Case("7410", "7400")
|
||||
.Case("7447", "7400")
|
||||
.Case("7455", "7450")
|
||||
.Case("G4", "g4")
|
||||
.Case("POWER4", "970")
|
||||
.Case("PPC970FX", "970")
|
||||
.Case("PPC970MP", "970")
|
||||
.Case("G5", "g5")
|
||||
.Case("POWER5", "g5")
|
||||
.Case("A2", "a2")
|
||||
.Case("POWER6", "pwr6")
|
||||
.Case("POWER7", "pwr7")
|
||||
.Case("POWER8", "pwr8")
|
||||
.Case("POWER8E", "pwr8")
|
||||
.Case("POWER9", "pwr9")
|
||||
.Default(generic);
|
||||
.Case("604e", "604e")
|
||||
.Case("604", "604")
|
||||
.Case("7400", "7400")
|
||||
.Case("7410", "7400")
|
||||
.Case("7447", "7400")
|
||||
.Case("7455", "7450")
|
||||
.Case("G4", "g4")
|
||||
.Case("POWER4", "970")
|
||||
.Case("PPC970FX", "970")
|
||||
.Case("PPC970MP", "970")
|
||||
.Case("G5", "g5")
|
||||
.Case("POWER5", "g5")
|
||||
.Case("A2", "a2")
|
||||
.Case("POWER6", "pwr6")
|
||||
.Case("POWER7", "pwr7")
|
||||
.Case("POWER8", "pwr8")
|
||||
.Case("POWER8E", "pwr8")
|
||||
.Case("POWER9", "pwr9")
|
||||
.Default(generic);
|
||||
}
|
||||
#elif defined(__linux__) && defined(__arm__)
|
||||
StringRef sys::getHostCPUName() {
|
||||
@ -656,18 +674,18 @@ StringRef sys::getHostCPUName() {
|
||||
// values correspond to the "Part number" in the CP15/c0 register. The
|
||||
// contents are specified in the various processor manuals.
|
||||
return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
|
||||
.Case("0x926", "arm926ej-s")
|
||||
.Case("0xb02", "mpcore")
|
||||
.Case("0xb36", "arm1136j-s")
|
||||
.Case("0xb56", "arm1156t2-s")
|
||||
.Case("0xb76", "arm1176jz-s")
|
||||
.Case("0xc08", "cortex-a8")
|
||||
.Case("0xc09", "cortex-a9")
|
||||
.Case("0xc0f", "cortex-a15")
|
||||
.Case("0xc20", "cortex-m0")
|
||||
.Case("0xc23", "cortex-m3")
|
||||
.Case("0xc24", "cortex-m4")
|
||||
.Default("generic");
|
||||
.Case("0x926", "arm926ej-s")
|
||||
.Case("0xb02", "mpcore")
|
||||
.Case("0xb36", "arm1136j-s")
|
||||
.Case("0xb56", "arm1156t2-s")
|
||||
.Case("0xb76", "arm1176jz-s")
|
||||
.Case("0xc08", "cortex-a8")
|
||||
.Case("0xc09", "cortex-a9")
|
||||
.Case("0xc0f", "cortex-a15")
|
||||
.Case("0xc20", "cortex-m0")
|
||||
.Case("0xc23", "cortex-m3")
|
||||
.Case("0xc24", "cortex-m4")
|
||||
.Default("generic");
|
||||
|
||||
if (Implementer == "0x51") // Qualcomm Technologies, Inc.
|
||||
// Look for the CPU part line.
|
||||
@ -677,8 +695,8 @@ StringRef sys::getHostCPUName() {
|
||||
// values correspond to the "Part number" in the CP15/c0 register. The
|
||||
// contents are specified in the various processor manuals.
|
||||
return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
|
||||
.Case("0x06f", "krait") // APQ8064
|
||||
.Default("generic");
|
||||
.Case("0x06f", "krait") // APQ8064
|
||||
.Default("generic");
|
||||
|
||||
return "generic";
|
||||
}
|
||||
@ -736,58 +754,57 @@ StringRef sys::getHostCPUName() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return "generic";
|
||||
}
|
||||
#else
|
||||
StringRef sys::getHostCPUName() {
|
||||
return "generic";
|
||||
}
|
||||
StringRef sys::getHostCPUName() { return "generic"; }
|
||||
#endif
|
||||
|
||||
#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
|
||||
|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
|
||||
#if defined(i386) || defined(__i386__) || defined(__x86__) || \
|
||||
defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \
|
||||
defined(_M_X64)
|
||||
bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
|
||||
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
|
||||
unsigned MaxLevel;
|
||||
union {
|
||||
unsigned u[3];
|
||||
char c[12];
|
||||
char c[12];
|
||||
} text;
|
||||
|
||||
if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
|
||||
if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
|
||||
MaxLevel < 1)
|
||||
return false;
|
||||
|
||||
GetX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
|
||||
|
||||
Features["cmov"] = (EDX >> 15) & 1;
|
||||
Features["mmx"] = (EDX >> 23) & 1;
|
||||
Features["sse"] = (EDX >> 25) & 1;
|
||||
Features["sse2"] = (EDX >> 26) & 1;
|
||||
Features["sse3"] = (ECX >> 0) & 1;
|
||||
Features["ssse3"] = (ECX >> 9) & 1;
|
||||
Features["cmov"] = (EDX >> 15) & 1;
|
||||
Features["mmx"] = (EDX >> 23) & 1;
|
||||
Features["sse"] = (EDX >> 25) & 1;
|
||||
Features["sse2"] = (EDX >> 26) & 1;
|
||||
Features["sse3"] = (ECX >> 0) & 1;
|
||||
Features["ssse3"] = (ECX >> 9) & 1;
|
||||
Features["sse4.1"] = (ECX >> 19) & 1;
|
||||
Features["sse4.2"] = (ECX >> 20) & 1;
|
||||
|
||||
Features["pclmul"] = (ECX >> 1) & 1;
|
||||
Features["cx16"] = (ECX >> 13) & 1;
|
||||
Features["movbe"] = (ECX >> 22) & 1;
|
||||
Features["pclmul"] = (ECX >> 1) & 1;
|
||||
Features["cx16"] = (ECX >> 13) & 1;
|
||||
Features["movbe"] = (ECX >> 22) & 1;
|
||||
Features["popcnt"] = (ECX >> 23) & 1;
|
||||
Features["aes"] = (ECX >> 25) & 1;
|
||||
Features["rdrnd"] = (ECX >> 30) & 1;
|
||||
Features["aes"] = (ECX >> 25) & 1;
|
||||
Features["rdrnd"] = (ECX >> 30) & 1;
|
||||
|
||||
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
|
||||
// indicates that the AVX registers will be saved and restored on context
|
||||
// switch, then we have full AVX support.
|
||||
bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
|
||||
!GetX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
|
||||
Features["avx"] = HasAVXSave;
|
||||
Features["fma"] = HasAVXSave && (ECX >> 12) & 1;
|
||||
Features["f16c"] = HasAVXSave && (ECX >> 29) & 1;
|
||||
Features["avx"] = HasAVXSave;
|
||||
Features["fma"] = HasAVXSave && (ECX >> 12) & 1;
|
||||
Features["f16c"] = HasAVXSave && (ECX >> 29) & 1;
|
||||
|
||||
// Only enable XSAVE if OS has enabled support for saving YMM state.
|
||||
Features["xsave"] = HasAVXSave && (ECX >> 26) & 1;
|
||||
Features["xsave"] = HasAVXSave && (ECX >> 26) & 1;
|
||||
|
||||
// AVX512 requires additional context to be saved by the OS.
|
||||
bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
|
||||
@ -797,37 +814,37 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
|
||||
|
||||
bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
|
||||
!GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
|
||||
Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
|
||||
Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
|
||||
Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
|
||||
Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
|
||||
Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
|
||||
Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
|
||||
Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
|
||||
Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
|
||||
Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
|
||||
Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
|
||||
Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
|
||||
Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
|
||||
Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
|
||||
|
||||
bool HasLeaf7 = MaxLevel >= 7 &&
|
||||
!GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
|
||||
bool HasLeaf7 =
|
||||
MaxLevel >= 7 && !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
|
||||
|
||||
// AVX2 is only supported if we have the OS save support from AVX.
|
||||
Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
|
||||
Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
|
||||
|
||||
Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
|
||||
Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
|
||||
Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
|
||||
Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
|
||||
Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
|
||||
Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
|
||||
Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
|
||||
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
|
||||
Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
|
||||
Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1);
|
||||
Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1);
|
||||
Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
|
||||
Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
|
||||
Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
|
||||
Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
|
||||
Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
|
||||
Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
|
||||
Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
|
||||
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
|
||||
Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
|
||||
Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1);
|
||||
Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1);
|
||||
Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
|
||||
Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
|
||||
Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
|
||||
Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
|
||||
Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
|
||||
|
||||
// AVX512 is only supported if the OS supports the context save for it.
|
||||
Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
|
||||
Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
|
||||
Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
|
||||
Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
|
||||
Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
|
||||
@ -837,17 +854,17 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
|
||||
Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
|
||||
|
||||
Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
|
||||
Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
|
||||
Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
|
||||
// Enable protection keys
|
||||
Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
|
||||
Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
|
||||
|
||||
bool HasLeafD = MaxLevel >= 0xd &&
|
||||
!GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
|
||||
!GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
|
||||
|
||||
// Only enable XSAVE if OS has enabled support for saving YMM state.
|
||||
Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1);
|
||||
Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1);
|
||||
Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1);
|
||||
Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1);
|
||||
Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1);
|
||||
|
||||
return true;
|
||||
}
|
||||
@ -876,31 +893,26 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
|
||||
|
||||
#if defined(__aarch64__)
|
||||
// Keep track of which crypto features we have seen
|
||||
enum {
|
||||
CAP_AES = 0x1,
|
||||
CAP_PMULL = 0x2,
|
||||
CAP_SHA1 = 0x4,
|
||||
CAP_SHA2 = 0x8
|
||||
};
|
||||
enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
|
||||
uint32_t crypto = 0;
|
||||
#endif
|
||||
|
||||
for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
|
||||
StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
|
||||
#if defined(__aarch64__)
|
||||
.Case("asimd", "neon")
|
||||
.Case("fp", "fp-armv8")
|
||||
.Case("crc32", "crc")
|
||||
.Case("asimd", "neon")
|
||||
.Case("fp", "fp-armv8")
|
||||
.Case("crc32", "crc")
|
||||
#else
|
||||
.Case("half", "fp16")
|
||||
.Case("neon", "neon")
|
||||
.Case("vfpv3", "vfp3")
|
||||
.Case("vfpv3d16", "d16")
|
||||
.Case("vfpv4", "vfp4")
|
||||
.Case("idiva", "hwdiv-arm")
|
||||
.Case("idivt", "hwdiv")
|
||||
.Case("half", "fp16")
|
||||
.Case("neon", "neon")
|
||||
.Case("vfpv3", "vfp3")
|
||||
.Case("vfpv3d16", "d16")
|
||||
.Case("vfpv4", "vfp4")
|
||||
.Case("idiva", "hwdiv-arm")
|
||||
.Case("idivt", "hwdiv")
|
||||
#endif
|
||||
.Default("");
|
||||
.Default("");
|
||||
|
||||
#if defined(__aarch64__)
|
||||
// We need to check crypto separately since we need all of the crypto
|
||||
@ -928,9 +940,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
|
||||
return true;
|
||||
}
|
||||
#else
|
||||
bool sys::getHostCPUFeatures(StringMap<bool> &Features){
|
||||
return false;
|
||||
}
|
||||
bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
|
||||
#endif
|
||||
|
||||
std::string sys::getProcessTriple() {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user