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This patch is in preparation for a substantial refactoring of the

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code. To make the diffs easier to read, clang-format everything first.

No functionality changed.

Patch by Alina Sbirlea!

http://reviews.llvm.org/D20926

llvm-svn: 271595
This commit is contained in:
Eric Christopher 2016-06-02 21:03:19 +00:00
parent 1c98eb67fa
commit f3784f237a
1 changed files with 303 additions and 293 deletions
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154
lib/Support/Host.cpp
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@ -33,9 +33,9 @@
#include <intrin.h> #include <intrin.h>
#endif #endif
#if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
#include <mach/host_info.h>
#include <mach/mach.h> #include <mach/mach.h>
#include <mach/mach_host.h> #include <mach/mach_host.h>
#include <mach/host_info.h>
#include <mach/machine.h> #include <mach/machine.h>
#endif #endif
@ -69,10 +69,12 @@ static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
} }
#endif #endif
#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ #if defined(i386) || defined(__i386__) || defined(__x86__) || \
|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \
defined(_M_X64)
/// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
/// the
/// specified arguments. If we can't run cpuid on the host, return true. /// specified arguments. If we can't run cpuid on the host, return true.
static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
unsigned *rECX, unsigned *rEDX) { unsigned *rECX, unsigned *rEDX) {
@ -82,20 +84,14 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
asm("movq\t%%rbx, %%rsi\n\t" asm("movq\t%%rbx, %%rsi\n\t"
"cpuid\n\t" "cpuid\n\t"
"xchgq\t%%rbx, %%rsi\n\t" "xchgq\t%%rbx, %%rsi\n\t"
: "=a" (*rEAX), : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
"=S" (*rEBX),
"=c" (*rECX),
"=d" (*rEDX)
: "a"(value)); : "a"(value));
return false; return false;
#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
asm("movl\t%%ebx, %%esi\n\t" asm("movl\t%%ebx, %%esi\n\t"
"cpuid\n\t" "cpuid\n\t"
"xchgl\t%%ebx, %%esi\n\t" "xchgl\t%%ebx, %%esi\n\t"
: "=a" (*rEAX), : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
"=S" (*rEBX),
"=c" (*rECX),
"=d" (*rEDX)
: "a"(value)); : "a"(value));
return false; return false;
// pedantic #else returns to appease -Wunreachable-code (so we don't generate // pedantic #else returns to appease -Wunreachable-code (so we don't generate
@ -117,7 +113,8 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
#endif #endif
} }
/// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
/// the
/// 4 values in the specified arguments. If we can't run cpuid on the host, /// 4 values in the specified arguments. If we can't run cpuid on the host,
/// return true. /// return true.
static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
@ -129,12 +126,8 @@ static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
asm("movq\t%%rbx, %%rsi\n\t" asm("movq\t%%rbx, %%rsi\n\t"
"cpuid\n\t" "cpuid\n\t"
"xchgq\t%%rbx, %%rsi\n\t" "xchgq\t%%rbx, %%rsi\n\t"
: "=a" (*rEAX), : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
"=S" (*rEBX), : "a"(value), "c"(subleaf));
"=c" (*rECX),
"=d" (*rEDX)
: "a" (value),
"c" (subleaf));
return false; return false;
#elif defined(_MSC_VER) #elif defined(_MSC_VER)
int registers[4]; int registers[4];
@ -152,12 +145,8 @@ static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
asm("movl\t%%ebx, %%esi\n\t" asm("movl\t%%ebx, %%esi\n\t"
"cpuid\n\t" "cpuid\n\t"
"xchgl\t%%ebx, %%esi\n\t" "xchgl\t%%ebx, %%esi\n\t"
: "=a" (*rEAX), : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
"=S" (*rEBX), : "a"(value), "c"(subleaf));
"=c" (*rECX),
"=d" (*rEDX)
: "a" (value),
"c" (subleaf));
return false; return false;
#elif defined(_MSC_VER) #elif defined(_MSC_VER)
__asm { __asm {
@ -243,8 +232,8 @@ StringRef sys::getHostCPUName() {
bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) && bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) &&
((EAX & 0x6) == 0x6); ((EAX & 0x6) == 0x6);
bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
bool HasLeaf7 = MaxLeaf >= 0x7 && bool HasLeaf7 =
!GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); MaxLeaf >= 0x7 && !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
@ -268,7 +257,8 @@ StringRef sys::getHostCPUName() {
case 5: // IntelSX2 processors case 5: // IntelSX2 processors
case 7: // Write-Back Enhanced IntelDX2 processors case 7: // Write-Back Enhanced IntelDX2 processors
case 8: // IntelDX4 OverDrive processors, IntelDX4 processors case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
default: return "i486"; default:
return "i486";
} }
case 5: case 5:
switch (Model) { switch (Model) {
@ -286,7 +276,8 @@ StringRef sys::getHostCPUName() {
// MMX technology (166, 200) // MMX technology (166, 200)
return "pentium-mmx"; return "pentium-mmx";
default: return "pentium"; default:
return "pentium";
} }
case 6: case 6:
switch (Model) { switch (Model) {
@ -308,7 +299,8 @@ StringRef sys::getHostCPUName() {
case 0x0b: // Pentium III processor, model 0Bh case 0x0b: // Pentium III processor, model 0Bh
return "pentium3"; return "pentium3";
case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. case 0x09: // Intel Pentium M processor, Intel Celeron M processor model
// 09.
case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
// 0Dh. All processors are manufactured using the 90 nm process. // 0Dh. All processors are manufactured using the 90 nm process.
case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
@ -332,7 +324,8 @@ StringRef sys::getHostCPUName() {
// 17h. All processors are manufactured using the 45 nm process. // 17h. All processors are manufactured using the 45 nm process.
// //
// 45nm: Penryn , Wolfdale, Yorkfield (XE) // 45nm: Penryn , Wolfdale, Yorkfield (XE)
case 0x1d: // Intel Xeon processor MP. All processors are manufactured using case 0x1d: // Intel Xeon processor MP. All processors are manufactured
// using
// the 45 nm process. // the 45 nm process.
return "penryn"; return "penryn";
@ -465,29 +458,41 @@ StringRef sys::getHostCPUName() {
case 5: case 5:
switch (Model) { switch (Model) {
case 6: case 6:
case 7: return "k6"; case 7:
case 8: return "k6-2"; return "k6";
case 8:
return "k6-2";
case 9: case 9:
case 13: return "k6-3"; case 13:
case 10: return "geode"; return "k6-3";
default: return "pentium"; case 10:
return "geode";
default:
return "pentium";
} }
case 6: case 6:
switch (Model) { switch (Model) {
case 4: return "athlon-tbird"; case 4:
return "athlon-tbird";
case 6: case 6:
case 7: case 7:
case 8: return "athlon-mp"; case 8:
case 10: return "athlon-xp"; return "athlon-mp";
default: return "athlon"; case 10:
return "athlon-xp";
default:
return "athlon";
} }
case 15: case 15:
if (HasSSE3) if (HasSSE3)
return "k8-sse3"; return "k8-sse3";
switch (Model) { switch (Model) {
case 1: return "opteron"; case 1:
case 5: return "athlon-fx"; // also opteron return "opteron";
default: return "athlon64"; case 5:
return "athlon-fx"; // also opteron
default:
return "athlon64";
} }
case 16: case 16:
return "amdfam10"; return "amdfam10";
@ -522,21 +527,34 @@ StringRef sys::getHostCPUName() {
host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
&infoCount); &infoCount);
if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic"; if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
return "generic";
switch (hostInfo.cpu_subtype) { switch (hostInfo.cpu_subtype) {
case CPU_SUBTYPE_POWERPC_601: return "601"; case CPU_SUBTYPE_POWERPC_601:
case CPU_SUBTYPE_POWERPC_602: return "602"; return "601";
case CPU_SUBTYPE_POWERPC_603: return "603"; case CPU_SUBTYPE_POWERPC_602:
case CPU_SUBTYPE_POWERPC_603e: return "603e"; return "602";
case CPU_SUBTYPE_POWERPC_603ev: return "603ev"; case CPU_SUBTYPE_POWERPC_603:
case CPU_SUBTYPE_POWERPC_604: return "604"; return "603";
case CPU_SUBTYPE_POWERPC_604e: return "604e"; case CPU_SUBTYPE_POWERPC_603e:
case CPU_SUBTYPE_POWERPC_620: return "620"; return "603e";
case CPU_SUBTYPE_POWERPC_750: return "750"; case CPU_SUBTYPE_POWERPC_603ev:
case CPU_SUBTYPE_POWERPC_7400: return "7400"; return "603ev";
case CPU_SUBTYPE_POWERPC_7450: return "7450"; case CPU_SUBTYPE_POWERPC_604:
case CPU_SUBTYPE_POWERPC_970: return "970"; return "604";
case CPU_SUBTYPE_POWERPC_604e:
return "604e";
case CPU_SUBTYPE_POWERPC_620:
return "620";
case CPU_SUBTYPE_POWERPC_750:
return "750";
case CPU_SUBTYPE_POWERPC_7400:
return "7400";
case CPU_SUBTYPE_POWERPC_7450:
return "7450";
case CPU_SUBTYPE_POWERPC_970:
return "970";
default:; default:;
} }
@ -740,13 +758,12 @@ StringRef sys::getHostCPUName() {
return "generic"; return "generic";
} }
#else #else
StringRef sys::getHostCPUName() { StringRef sys::getHostCPUName() { return "generic"; }
return "generic";
}
#endif #endif
#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ #if defined(i386) || defined(__i386__) || defined(__x86__) || \
|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \
defined(_M_X64)
bool sys::getHostCPUFeatures(StringMap<bool> &Features) { bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
unsigned MaxLevel; unsigned MaxLevel;
@ -805,8 +822,8 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
bool HasLeaf7 = MaxLevel >= 7 && bool HasLeaf7 =
!GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); MaxLevel >= 7 && !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
// AVX2 is only supported if we have the OS save support from AVX. // AVX2 is only supported if we have the OS save support from AVX.
Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
@ -876,12 +893,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
#if defined(__aarch64__) #if defined(__aarch64__)
// Keep track of which crypto features we have seen // Keep track of which crypto features we have seen
enum { enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
CAP_AES = 0x1,
CAP_PMULL = 0x2,
CAP_SHA1 = 0x4,
CAP_SHA2 = 0x8
};
uint32_t crypto = 0; uint32_t crypto = 0;
#endif #endif
@ -928,9 +940,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
return true; return true;
} }
#else #else
bool sys::getHostCPUFeatures(StringMap<bool> &Features){ bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
return false;
}
#endif #endif
std::string sys::getProcessTriple() { std::string sys::getProcessTriple() {