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This patch is in preparation for a substantial refactoring of the

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code. To make the diffs easier to read, clang-format everything first.

No functionality changed.

Patch by Alina Sbirlea!

http://reviews.llvm.org/D20926

llvm-svn: 271595
This commit is contained in:
Eric Christopher 2016-06-02 21:03:19 +00:00
parent 1c98eb67fa
commit f3784f237a
1 changed files with 303 additions and 293 deletions
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596
lib/Support/Host.cpp
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@ -33,9 +33,9 @@
#include <intrin.h> #include <intrin.h>
#endif #endif
#if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
#include <mach/host_info.h>
#include <mach/mach.h> #include <mach/mach.h>
#include <mach/mach_host.h> #include <mach/mach_host.h>
#include <mach/host_info.h>
#include <mach/machine.h> #include <mach/machine.h>
#endif #endif
@ -69,40 +69,36 @@ static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
} }
#endif #endif
#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ #if defined(i386) || defined(__i386__) || defined(__x86__) || \
|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \
defined(_M_X64)
/// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
/// the
/// specified arguments. If we can't run cpuid on the host, return true. /// specified arguments. If we can't run cpuid on the host, return true.
static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
unsigned *rECX, unsigned *rEDX) { unsigned *rECX, unsigned *rEDX) {
#if defined(__GNUC__) || defined(__clang__) #if defined(__GNUC__) || defined(__clang__)
#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
asm ("movq\t%%rbx, %%rsi\n\t" asm("movq\t%%rbx, %%rsi\n\t"
"cpuid\n\t" "cpuid\n\t"
"xchgq\t%%rbx, %%rsi\n\t" "xchgq\t%%rbx, %%rsi\n\t"
: "=a" (*rEAX), : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
"=S" (*rEBX), : "a"(value));
"=c" (*rECX), return false;
"=d" (*rEDX) #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
: "a" (value)); asm("movl\t%%ebx, %%esi\n\t"
return false; "cpuid\n\t"
#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) "xchgl\t%%ebx, %%esi\n\t"
asm ("movl\t%%ebx, %%esi\n\t" : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
"cpuid\n\t" : "a"(value));
"xchgl\t%%ebx, %%esi\n\t" return false;
: "=a" (*rEAX),
"=S" (*rEBX),
"=c" (*rECX),
"=d" (*rEDX)
: "a" (value));
return false;
// pedantic #else returns to appease -Wunreachable-code (so we don't generate // pedantic #else returns to appease -Wunreachable-code (so we don't generate
// postprocessed code that looks like "return true; return false;") // postprocessed code that looks like "return true; return false;")
#else #else
return true; return true;
#endif #endif
#elif defined(_MSC_VER) #elif defined(_MSC_VER)
// The MSVC intrinsic is portable across x86 and x64. // The MSVC intrinsic is portable across x86 and x64.
int registers[4]; int registers[4];
@ -117,50 +113,43 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
#endif #endif
} }
/// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
/// the
/// 4 values in the specified arguments. If we can't run cpuid on the host, /// 4 values in the specified arguments. If we can't run cpuid on the host,
/// return true. /// return true.
static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
unsigned *rEAX, unsigned *rEBX, unsigned *rECX, unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
unsigned *rEDX) { unsigned *rEDX) {
#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
#if defined(__GNUC__) #if defined(__GNUC__)
// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
asm ("movq\t%%rbx, %%rsi\n\t" asm("movq\t%%rbx, %%rsi\n\t"
"cpuid\n\t" "cpuid\n\t"
"xchgq\t%%rbx, %%rsi\n\t" "xchgq\t%%rbx, %%rsi\n\t"
: "=a" (*rEAX), : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
"=S" (*rEBX), : "a"(value), "c"(subleaf));
"=c" (*rECX), return false;
"=d" (*rEDX) #elif defined(_MSC_VER)
: "a" (value), int registers[4];
"c" (subleaf)); __cpuidex(registers, value, subleaf);
return false; *rEAX = registers[0];
#elif defined(_MSC_VER) *rEBX = registers[1];
int registers[4]; *rECX = registers[2];
__cpuidex(registers, value, subleaf); *rEDX = registers[3];
*rEAX = registers[0]; return false;
*rEBX = registers[1]; #else
*rECX = registers[2]; return true;
*rEDX = registers[3]; #endif
return false;
#else
return true;
#endif
#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
#if defined(__GNUC__) #if defined(__GNUC__)
asm ("movl\t%%ebx, %%esi\n\t" asm("movl\t%%ebx, %%esi\n\t"
"cpuid\n\t" "cpuid\n\t"
"xchgl\t%%ebx, %%esi\n\t" "xchgl\t%%ebx, %%esi\n\t"
: "=a" (*rEAX), : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
"=S" (*rEBX), : "a"(value), "c"(subleaf));
"=c" (*rECX), return false;
"=d" (*rEDX) #elif defined(_MSC_VER)
: "a" (value), __asm {
"c" (subleaf));
return false;
#elif defined(_MSC_VER)
__asm {
mov eax,value mov eax,value
mov ecx,subleaf mov ecx,subleaf
cpuid cpuid
@ -172,11 +161,11 @@ static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
mov dword ptr [esi],ecx mov dword ptr [esi],ecx
mov esi,rEDX mov esi,rEDX
mov dword ptr [esi],edx mov dword ptr [esi],edx
} }
return false; return false;
#else #else
return true; return true;
#endif #endif
#else #else
return true; return true;
#endif #endif
@ -187,7 +176,7 @@ static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) {
// Check xgetbv; this uses a .byte sequence instead of the instruction // Check xgetbv; this uses a .byte sequence instead of the instruction
// directly because older assemblers do not include support for xgetbv and // directly because older assemblers do not include support for xgetbv and
// there is no easy way to conditionally compile based on the assembler used. // there is no easy way to conditionally compile based on the assembler used.
__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (*rEAX), "=d" (*rEDX) : "c" (0)); __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
return false; return false;
#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
@ -202,11 +191,11 @@ static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) {
static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
unsigned &Model) { unsigned &Model) {
Family = (EAX >> 8) & 0xf; // Bits 8 - 11 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
Model = (EAX >> 4) & 0xf; // Bits 4 - 7 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
if (Family == 6 || Family == 0xf) { if (Family == 6 || Family == 0xf) {
if (Family == 0xf) if (Family == 0xf)
// Examine extended family ID if family ID is F. // Examine extended family ID if family ID is F.
Family += (EAX >> 20) & 0xff; // Bits 20 - 27 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
// Examine extended model ID if family ID is 6 or F. // Examine extended model ID if family ID is 6 or F.
Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
} }
@ -217,22 +206,22 @@ StringRef sys::getHostCPUName() {
if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
return "generic"; return "generic";
unsigned Family = 0; unsigned Family = 0;
unsigned Model = 0; unsigned Model = 0;
DetectX86FamilyModel(EAX, Family, Model); DetectX86FamilyModel(EAX, Family, Model);
union { union {
unsigned u[3]; unsigned u[3];
char c[12]; char c[12];
} text; } text;
unsigned MaxLeaf; unsigned MaxLeaf;
GetX86CpuIDAndInfo(0, &MaxLeaf, text.u+0, text.u+2, text.u+1); GetX86CpuIDAndInfo(0, &MaxLeaf, text.u + 0, text.u + 2, text.u + 1);
bool HasMMX = (EDX >> 23) & 1; bool HasMMX = (EDX >> 23) & 1;
bool HasSSE = (EDX >> 25) & 1; bool HasSSE = (EDX >> 25) & 1;
bool HasSSE2 = (EDX >> 26) & 1; bool HasSSE2 = (EDX >> 26) & 1;
bool HasSSE3 = (ECX >> 0) & 1; bool HasSSE3 = (ECX >> 0) & 1;
bool HasSSSE3 = (ECX >> 9) & 1; bool HasSSSE3 = (ECX >> 9) & 1;
bool HasSSE41 = (ECX >> 19) & 1; bool HasSSE41 = (ECX >> 19) & 1;
bool HasSSE42 = (ECX >> 20) & 1; bool HasSSE42 = (ECX >> 20) & 1;
bool HasMOVBE = (ECX >> 22) & 1; bool HasMOVBE = (ECX >> 22) & 1;
@ -243,8 +232,8 @@ StringRef sys::getHostCPUName() {
bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) && bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) &&
((EAX & 0x6) == 0x6); ((EAX & 0x6) == 0x6);
bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
bool HasLeaf7 = MaxLeaf >= 0x7 && bool HasLeaf7 =
!GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); MaxLeaf >= 0x7 && !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
@ -268,25 +257,27 @@ StringRef sys::getHostCPUName() {
case 5: // IntelSX2 processors case 5: // IntelSX2 processors
case 7: // Write-Back Enhanced IntelDX2 processors case 7: // Write-Back Enhanced IntelDX2 processors
case 8: // IntelDX4 OverDrive processors, IntelDX4 processors case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
default: return "i486"; default:
return "i486";
} }
case 5: case 5:
switch (Model) { switch (Model) {
case 1: // Pentium OverDrive processor for Pentium processor (60, 66), case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
// Pentium processors (60, 66) // Pentium processors (60, 66)
case 2: // Pentium OverDrive processor for Pentium processor (75, 90, case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
// 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
// 150, 166, 200) // 150, 166, 200)
case 3: // Pentium OverDrive processors for Intel486 processor-based case 3: // Pentium OverDrive processors for Intel486 processor-based
// systems // systems
return "pentium"; return "pentium";
case 4: // Pentium OverDrive processor with MMX technology for Pentium case 4: // Pentium OverDrive processor with MMX technology for Pentium
// processor (75, 90, 100, 120, 133), Pentium processor with // processor (75, 90, 100, 120, 133), Pentium processor with
// MMX technology (166, 200) // MMX technology (166, 200)
return "pentium-mmx"; return "pentium-mmx";
default: return "pentium"; default:
return "pentium";
} }
case 6: case 6:
switch (Model) { switch (Model) {
@ -308,31 +299,33 @@ StringRef sys::getHostCPUName() {
case 0x0b: // Pentium III processor, model 0Bh case 0x0b: // Pentium III processor, model 0Bh
return "pentium3"; return "pentium3";
case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. case 0x09: // Intel Pentium M processor, Intel Celeron M processor model
// 09.
case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
// 0Dh. All processors are manufactured using the 90 nm process. // 0Dh. All processors are manufactured using the 90 nm process.
case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
// Integrated Processor with Intel QuickAssist Technology // Integrated Processor with Intel QuickAssist Technology
return "pentium-m"; return "pentium-m";
case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
// 0Eh. All processors are manufactured using the 65 nm process. // 0Eh. All processors are manufactured using the 65 nm process.
return "yonah"; return "yonah";
case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
// processor, Intel Core 2 Quad processor, Intel Core 2 Quad // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
// mobile processor, Intel Core 2 Extreme processor, Intel // mobile processor, Intel Core 2 Extreme processor, Intel
// Pentium Dual-Core processor, Intel Xeon processor, model // Pentium Dual-Core processor, Intel Xeon processor, model
// 0Fh. All processors are manufactured using the 65 nm process. // 0Fh. All processors are manufactured using the 65 nm process.
case 0x16: // Intel Celeron processor model 16h. All processors are case 0x16: // Intel Celeron processor model 16h. All processors are
// manufactured using the 65 nm process // manufactured using the 65 nm process
return "core2"; return "core2";
case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
// 17h. All processors are manufactured using the 45 nm process. // 17h. All processors are manufactured using the 45 nm process.
// //
// 45nm: Penryn , Wolfdale, Yorkfield (XE) // 45nm: Penryn , Wolfdale, Yorkfield (XE)
case 0x1d: // Intel Xeon processor MP. All processors are manufactured using case 0x1d: // Intel Xeon processor MP. All processors are manufactured
// using
// the 45 nm process. // the 45 nm process.
return "penryn"; return "penryn";
@ -423,28 +416,28 @@ StringRef sys::getHostCPUName() {
} }
case 15: { case 15: {
switch (Model) { switch (Model) {
case 0: // Pentium 4 processor, Intel Xeon processor. All processors are case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
// model 00h and manufactured using the 0.18 micron process. // model 00h and manufactured using the 0.18 micron process.
case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
// processor MP, and Intel Celeron processor. All processors are // processor MP, and Intel Celeron processor. All processors are
// model 01h and manufactured using the 0.18 micron process. // model 01h and manufactured using the 0.18 micron process.
case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
// Intel Xeon processor, Intel Xeon processor MP, Intel Celeron // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
// processor, and Mobile Intel Celeron processor. All processors // processor, and Mobile Intel Celeron processor. All processors
// are model 02h and manufactured using the 0.13 micron process. // are model 02h and manufactured using the 0.13 micron process.
return (Em64T) ? "x86-64" : "pentium4"; return (Em64T) ? "x86-64" : "pentium4";
case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
// processor. All processors are model 03h and manufactured using // processor. All processors are model 03h and manufactured using
// the 90 nm process. // the 90 nm process.
case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
// Pentium D processor, Intel Xeon processor, Intel Xeon // Pentium D processor, Intel Xeon processor, Intel Xeon
// processor MP, Intel Celeron D processor. All processors are // processor MP, Intel Celeron D processor. All processors are
// model 04h and manufactured using the 90 nm process. // model 04h and manufactured using the 90 nm process.
case 6: // Pentium 4 processor, Pentium D processor, Pentium processor case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
// Extreme Edition, Intel Xeon processor, Intel Xeon processor // Extreme Edition, Intel Xeon processor, Intel Xeon processor
// MP, Intel Celeron D processor. All processors are model 06h // MP, Intel Celeron D processor. All processors are model 06h
// and manufactured using the 65 nm process. // and manufactured using the 65 nm process.
return (Em64T) ? "nocona" : "prescott"; return (Em64T) ? "nocona" : "prescott";
default: default:
@ -460,53 +453,65 @@ StringRef sys::getHostCPUName() {
// appears to be no way to generate the wide variety of AMD-specific targets // appears to be no way to generate the wide variety of AMD-specific targets
// from the information returned from CPUID. // from the information returned from CPUID.
switch (Family) { switch (Family) {
case 4: case 4:
return "i486"; return "i486";
case 5: case 5:
switch (Model) { switch (Model) {
case 6:
case 7: return "k6";
case 8: return "k6-2";
case 9:
case 13: return "k6-3";
case 10: return "geode";
default: return "pentium";
}
case 6: case 6:
switch (Model) { case 7:
case 4: return "athlon-tbird"; return "k6";
case 6: case 8:
case 7: return "k6-2";
case 8: return "athlon-mp"; case 9:
case 10: return "athlon-xp"; case 13:
default: return "athlon"; return "k6-3";
} case 10:
case 15: return "geode";
if (HasSSE3) default:
return "k8-sse3"; return "pentium";
switch (Model) { }
case 1: return "opteron"; case 6:
case 5: return "athlon-fx"; // also opteron switch (Model) {
default: return "athlon64"; case 4:
} return "athlon-tbird";
case 16: case 6:
return "amdfam10"; case 7:
case 20: case 8:
return "athlon-mp";
case 10:
return "athlon-xp";
default:
return "athlon";
}
case 15:
if (HasSSE3)
return "k8-sse3";
switch (Model) {
case 1:
return "opteron";
case 5:
return "athlon-fx"; // also opteron
default:
return "athlon64";
}
case 16:
return "amdfam10";
case 20:
return "btver1";
case 21:
if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
return "btver1"; return "btver1";
case 21: if (Model >= 0x50)
if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback. return "bdver4"; // 50h-6Fh: Excavator
return "btver1"; if (Model >= 0x30)
if (Model >= 0x50) return "bdver3"; // 30h-3Fh: Steamroller
return "bdver4"; // 50h-6Fh: Excavator if (Model >= 0x10 || HasTBM)
if (Model >= 0x30) return "bdver2"; // 10h-1Fh: Piledriver
return "bdver3"; // 30h-3Fh: Steamroller return "bdver1"; // 00h-0Fh: Bulldozer
if (Model >= 0x10 || HasTBM) case 22:
return "bdver2"; // 10h-1Fh: Piledriver if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
return "bdver1"; // 00h-0Fh: Bulldozer return "btver1";
case 22: return "btver2";
if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
return "btver1";
return "btver2";
default: default:
return "generic"; return "generic";
} }
@ -519,27 +524,40 @@ StringRef sys::getHostCPUName() {
mach_msg_type_number_t infoCount; mach_msg_type_number_t infoCount;
infoCount = HOST_BASIC_INFO_COUNT; infoCount = HOST_BASIC_INFO_COUNT;
host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
&infoCount); &infoCount);
if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
switch(hostInfo.cpu_subtype) { if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
case CPU_SUBTYPE_POWERPC_601: return "601"; return "generic";
case CPU_SUBTYPE_POWERPC_602: return "602";
case CPU_SUBTYPE_POWERPC_603: return "603"; switch (hostInfo.cpu_subtype) {
case CPU_SUBTYPE_POWERPC_603e: return "603e"; case CPU_SUBTYPE_POWERPC_601:
case CPU_SUBTYPE_POWERPC_603ev: return "603ev"; return "601";
case CPU_SUBTYPE_POWERPC_604: return "604"; case CPU_SUBTYPE_POWERPC_602:
case CPU_SUBTYPE_POWERPC_604e: return "604e"; return "602";
case CPU_SUBTYPE_POWERPC_620: return "620"; case CPU_SUBTYPE_POWERPC_603:
case CPU_SUBTYPE_POWERPC_750: return "750"; return "603";
case CPU_SUBTYPE_POWERPC_7400: return "7400"; case CPU_SUBTYPE_POWERPC_603e:
case CPU_SUBTYPE_POWERPC_7450: return "7450"; return "603e";
case CPU_SUBTYPE_POWERPC_970: return "970"; case CPU_SUBTYPE_POWERPC_603ev:
default: ; return "603ev";
case CPU_SUBTYPE_POWERPC_604:
return "604";
case CPU_SUBTYPE_POWERPC_604e:
return "604e";
case CPU_SUBTYPE_POWERPC_620:
return "620";
case CPU_SUBTYPE_POWERPC_750:
return "750";
case CPU_SUBTYPE_POWERPC_7400:
return "7400";
case CPU_SUBTYPE_POWERPC_7450:
return "7450";
case CPU_SUBTYPE_POWERPC_970:
return "970";
default:;
} }
return "generic"; return "generic";
} }
#elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
@ -578,12 +596,12 @@ StringRef sys::getHostCPUName() {
++CIP; ++CIP;
while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
++CIP; ++CIP;
if (CIP < CPUInfoEnd && *CIP == ':') { if (CIP < CPUInfoEnd && *CIP == ':') {
++CIP; ++CIP;
while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
++CIP; ++CIP;
if (CIP < CPUInfoEnd) { if (CIP < CPUInfoEnd) {
CPUStart = CIP; CPUStart = CIP;
while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
@ -605,25 +623,25 @@ StringRef sys::getHostCPUName() {
return generic; return generic;
return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
.Case("604e", "604e") .Case("604e", "604e")
.Case("604", "604") .Case("604", "604")
.Case("7400", "7400") .Case("7400", "7400")
.Case("7410", "7400") .Case("7410", "7400")
.Case("7447", "7400") .Case("7447", "7400")
.Case("7455", "7450") .Case("7455", "7450")
.Case("G4", "g4") .Case("G4", "g4")
.Case("POWER4", "970") .Case("POWER4", "970")
.Case("PPC970FX", "970") .Case("PPC970FX", "970")
.Case("PPC970MP", "970") .Case("PPC970MP", "970")
.Case("G5", "g5") .Case("G5", "g5")
.Case("POWER5", "g5") .Case("POWER5", "g5")
.Case("A2", "a2") .Case("A2", "a2")
.Case("POWER6", "pwr6") .Case("POWER6", "pwr6")
.Case("POWER7", "pwr7") .Case("POWER7", "pwr7")
.Case("POWER8", "pwr8") .Case("POWER8", "pwr8")
.Case("POWER8E", "pwr8") .Case("POWER8E", "pwr8")
.Case("POWER9", "pwr9") .Case("POWER9", "pwr9")
.Default(generic); .Default(generic);
} }
#elif defined(__linux__) && defined(__arm__) #elif defined(__linux__) && defined(__arm__)
StringRef sys::getHostCPUName() { StringRef sys::getHostCPUName() {
@ -656,18 +674,18 @@ StringRef sys::getHostCPUName() {
// values correspond to the "Part number" in the CP15/c0 register. The // values correspond to the "Part number" in the CP15/c0 register. The
// contents are specified in the various processor manuals. // contents are specified in the various processor manuals.
return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
.Case("0x926", "arm926ej-s") .Case("0x926", "arm926ej-s")
.Case("0xb02", "mpcore") .Case("0xb02", "mpcore")
.Case("0xb36", "arm1136j-s") .Case("0xb36", "arm1136j-s")
.Case("0xb56", "arm1156t2-s") .Case("0xb56", "arm1156t2-s")
.Case("0xb76", "arm1176jz-s") .Case("0xb76", "arm1176jz-s")
.Case("0xc08", "cortex-a8") .Case("0xc08", "cortex-a8")
.Case("0xc09", "cortex-a9") .Case("0xc09", "cortex-a9")
.Case("0xc0f", "cortex-a15") .Case("0xc0f", "cortex-a15")
.Case("0xc20", "cortex-m0") .Case("0xc20", "cortex-m0")
.Case("0xc23", "cortex-m3") .Case("0xc23", "cortex-m3")
.Case("0xc24", "cortex-m4") .Case("0xc24", "cortex-m4")
.Default("generic"); .Default("generic");
if (Implementer == "0x51") // Qualcomm Technologies, Inc. if (Implementer == "0x51") // Qualcomm Technologies, Inc.
// Look for the CPU part line. // Look for the CPU part line.
@ -677,8 +695,8 @@ StringRef sys::getHostCPUName() {
// values correspond to the "Part number" in the CP15/c0 register. The // values correspond to the "Part number" in the CP15/c0 register. The
// contents are specified in the various processor manuals. // contents are specified in the various processor manuals.
return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
.Case("0x06f", "krait") // APQ8064 .Case("0x06f", "krait") // APQ8064
.Default("generic"); .Default("generic");
return "generic"; return "generic";
} }
@ -736,58 +754,57 @@ StringRef sys::getHostCPUName() {
break; break;
} }
} }
return "generic"; return "generic";
} }
#else #else
StringRef sys::getHostCPUName() { StringRef sys::getHostCPUName() { return "generic"; }
return "generic";
}
#endif #endif
#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ #if defined(i386) || defined(__i386__) || defined(__x86__) || \
|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \
defined(_M_X64)
bool sys::getHostCPUFeatures(StringMap<bool> &Features) { bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
unsigned MaxLevel; unsigned MaxLevel;
union { union {
unsigned u[3]; unsigned u[3];
char c[12]; char c[12];
} text; } text;
if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) || if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
MaxLevel < 1) MaxLevel < 1)
return false; return false;
GetX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); GetX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
Features["cmov"] = (EDX >> 15) & 1; Features["cmov"] = (EDX >> 15) & 1;
Features["mmx"] = (EDX >> 23) & 1; Features["mmx"] = (EDX >> 23) & 1;
Features["sse"] = (EDX >> 25) & 1; Features["sse"] = (EDX >> 25) & 1;
Features["sse2"] = (EDX >> 26) & 1; Features["sse2"] = (EDX >> 26) & 1;
Features["sse3"] = (ECX >> 0) & 1; Features["sse3"] = (ECX >> 0) & 1;
Features["ssse3"] = (ECX >> 9) & 1; Features["ssse3"] = (ECX >> 9) & 1;
Features["sse4.1"] = (ECX >> 19) & 1; Features["sse4.1"] = (ECX >> 19) & 1;
Features["sse4.2"] = (ECX >> 20) & 1; Features["sse4.2"] = (ECX >> 20) & 1;
Features["pclmul"] = (ECX >> 1) & 1; Features["pclmul"] = (ECX >> 1) & 1;
Features["cx16"] = (ECX >> 13) & 1; Features["cx16"] = (ECX >> 13) & 1;
Features["movbe"] = (ECX >> 22) & 1; Features["movbe"] = (ECX >> 22) & 1;
Features["popcnt"] = (ECX >> 23) & 1; Features["popcnt"] = (ECX >> 23) & 1;
Features["aes"] = (ECX >> 25) & 1; Features["aes"] = (ECX >> 25) & 1;
Features["rdrnd"] = (ECX >> 30) & 1; Features["rdrnd"] = (ECX >> 30) & 1;
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
// indicates that the AVX registers will be saved and restored on context // indicates that the AVX registers will be saved and restored on context
// switch, then we have full AVX support. // switch, then we have full AVX support.
bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
!GetX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); !GetX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
Features["avx"] = HasAVXSave; Features["avx"] = HasAVXSave;
Features["fma"] = HasAVXSave && (ECX >> 12) & 1; Features["fma"] = HasAVXSave && (ECX >> 12) & 1;
Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; Features["f16c"] = HasAVXSave && (ECX >> 29) & 1;
// Only enable XSAVE if OS has enabled support for saving YMM state. // Only enable XSAVE if OS has enabled support for saving YMM state.
Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; Features["xsave"] = HasAVXSave && (ECX >> 26) & 1;
// AVX512 requires additional context to be saved by the OS. // AVX512 requires additional context to be saved by the OS.
bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
@ -797,37 +814,37 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
!GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); !GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
bool HasLeaf7 = MaxLevel >= 7 && bool HasLeaf7 =
!GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); MaxLevel >= 7 && !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
// AVX2 is only supported if we have the OS save support from AVX. // AVX2 is only supported if we have the OS save support from AVX.
Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1); Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1); Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1);
Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1); Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1);
Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
// AVX512 is only supported if the OS supports the context save for it. // AVX512 is only supported if the OS supports the context save for it.
Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
@ -837,17 +854,17 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
// Enable protection keys // Enable protection keys
Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
bool HasLeafD = MaxLevel >= 0xd && bool HasLeafD = MaxLevel >= 0xd &&
!GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); !GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
// Only enable XSAVE if OS has enabled support for saving YMM state. // Only enable XSAVE if OS has enabled support for saving YMM state.
Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1);
Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1);
Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1);
return true; return true;
} }
@ -876,31 +893,26 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
#if defined(__aarch64__) #if defined(__aarch64__)
// Keep track of which crypto features we have seen // Keep track of which crypto features we have seen
enum { enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
CAP_AES = 0x1,
CAP_PMULL = 0x2,
CAP_SHA1 = 0x4,
CAP_SHA2 = 0x8
};
uint32_t crypto = 0; uint32_t crypto = 0;
#endif #endif
for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
#if defined(__aarch64__) #if defined(__aarch64__)
.Case("asimd", "neon") .Case("asimd", "neon")
.Case("fp", "fp-armv8") .Case("fp", "fp-armv8")
.Case("crc32", "crc") .Case("crc32", "crc")
#else #else
.Case("half", "fp16") .Case("half", "fp16")
.Case("neon", "neon") .Case("neon", "neon")
.Case("vfpv3", "vfp3") .Case("vfpv3", "vfp3")
.Case("vfpv3d16", "d16") .Case("vfpv3d16", "d16")
.Case("vfpv4", "vfp4") .Case("vfpv4", "vfp4")
.Case("idiva", "hwdiv-arm") .Case("idiva", "hwdiv-arm")
.Case("idivt", "hwdiv") .Case("idivt", "hwdiv")
#endif #endif
.Default(""); .Default("");
#if defined(__aarch64__) #if defined(__aarch64__)
// We need to check crypto separately since we need all of the crypto // We need to check crypto separately since we need all of the crypto
@ -928,9 +940,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
return true; return true;
} }
#else #else
bool sys::getHostCPUFeatures(StringMap<bool> &Features){ bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
return false;
}
#endif #endif
std::string sys::getProcessTriple() { std::string sys::getProcessTriple() {