mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 19:12:56 +02:00
Remove trailing whitespace. Reorder some methods
and cases alphabetically. No functionality change. llvm-svn: 75001
This commit is contained in:
parent
1e5ec149bb
commit
f3d675f3dd
@ -491,7 +491,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
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SDValue NewVAARG;
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SDValue NewVAARG;
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NewVAARG = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2));
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NewVAARG = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2));
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// Legalized the chain result - switch anything that used the old chain to
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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// use the new one.
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ReplaceValueWith(SDValue(N, 1), NewVAARG.getValue(1));
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ReplaceValueWith(SDValue(N, 1), NewVAARG.getValue(1));
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@ -359,7 +359,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
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// If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
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// If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
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// not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
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// not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
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// and SINT conversions are Custom, there is no way to tell which is preferable.
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// and SINT conversions are Custom, there is no way to tell which is preferable.
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// We choose SINT because that's the right thing on PPC.)
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// We choose SINT because that's the right thing on PPC.)
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if (N->getOpcode() == ISD::FP_TO_UINT &&
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if (N->getOpcode() == ISD::FP_TO_UINT &&
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!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
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!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
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TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
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TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
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@ -1838,7 +1838,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
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else if (VT == MVT::i128)
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else if (VT == MVT::i128)
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LC = RTLIB::SRA_I128;
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LC = RTLIB::SRA_I128;
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}
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}
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if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
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if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
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SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
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SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
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SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
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SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
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@ -517,10 +517,10 @@ private:
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SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
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SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
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SDValue ScalarizeVecRes_SELECT(SDNode *N);
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SDValue ScalarizeVecRes_SELECT(SDNode *N);
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SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
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SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
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SDValue ScalarizeVecRes_SETCC(SDNode *N);
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SDValue ScalarizeVecRes_UNDEF(SDNode *N);
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SDValue ScalarizeVecRes_UNDEF(SDNode *N);
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SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
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SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
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SDValue ScalarizeVecRes_VSETCC(SDNode *N);
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SDValue ScalarizeVecRes_VSETCC(SDNode *N);
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SDValue ScalarizeVecRes_SETCC(SDNode *N);
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// Vector Operand Scalarization: <1 x ty> -> ty.
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// Vector Operand Scalarization: <1 x ty> -> ty.
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bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
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bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
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@ -558,10 +558,10 @@ private:
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void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
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SDValue &Hi);
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void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
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SDValue &Hi);
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// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
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// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
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bool SplitVectorOperand(SDNode *N, unsigned OpNo);
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bool SplitVectorOperand(SDNode *N, unsigned OpNo);
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@ -106,7 +106,7 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
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if (TLI.isBigEndian())
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if (TLI.isBigEndian())
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std::swap(Lo, Hi);
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std::swap(Lo, Hi);
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return;
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return;
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}
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}
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}
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}
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@ -53,10 +53,10 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
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case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
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case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
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case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
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case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
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case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
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case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
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case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
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case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
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case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
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case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
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case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
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case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
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case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
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case ISD::CTLZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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case ISD::CTPOP:
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@ -207,6 +207,15 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
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N->getOperand(4));
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N->getOperand(4));
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}
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(0));
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SDValue RHS = GetScalarizedVector(N->getOperand(1));
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DebugLoc DL = N->getDebugLoc();
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// Turn it into a scalar SETCC.
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return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
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SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
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return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
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return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
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}
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}
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@ -242,7 +251,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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// Truncate to the final type.
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// Truncate to the final type.
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return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
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return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
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}
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}
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// The SETCC result type is smaller than the vector element type.
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// The SETCC result type is smaller than the vector element type.
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// If the SetCC result is not sign-extended, chop it down to MVT::i1.
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// If the SetCC result is not sign-extended, chop it down to MVT::i1.
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if (TLI.getBooleanContents() !=
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if (TLI.getBooleanContents() !=
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@ -251,14 +260,6 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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// Sign extend to the final type.
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// Sign extend to the final type.
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return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
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return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
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}
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(0));
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SDValue RHS = GetScalarizedVector(N->getOperand(1));
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DebugLoc DL = N->getDebugLoc();
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// Turn it into a scalar SETCC.
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return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -392,14 +393,13 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::LOAD:
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case ISD::LOAD:
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SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
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SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
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break;
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break;
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case ISD::SETCC:
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case ISD::VSETCC:
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SplitVecRes_SETCC(N, Lo, Hi);
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break;
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case ISD::VECTOR_SHUFFLE:
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case ISD::VECTOR_SHUFFLE:
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SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
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SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
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break;
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break;
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case ISD::VSETCC:
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case ISD::SETCC:
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SplitVecRes_SETCC(N, Lo, Hi);
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break;
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case ISD::CTTZ:
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTLZ:
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@ -735,6 +735,42 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
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ReplaceValueWith(SDValue(LD, 1), Ch);
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ReplaceValueWith(SDValue(LD, 1), Ch);
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}
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}
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void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
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MVT LoVT, HiVT;
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DebugLoc DL = N->getDebugLoc();
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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// Split the input.
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MVT InVT = N->getOperand(0).getValueType();
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SDValue LL, LH, RL, RH;
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switch (getTypeAction(InVT)) {
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default: assert(0 && "Unexpected type action!");
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case WidenVector: assert(0 && "Unimp");
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case Legal: {
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assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
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MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
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LoVT.getVectorNumElements());
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LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
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DAG.getIntPtrConstant(0));
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LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
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DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
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RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
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DAG.getIntPtrConstant(0));
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RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
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DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
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break;
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}
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case SplitVector:
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GetSplitVector(N->getOperand(0), LL, LH);
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GetSplitVector(N->getOperand(1), RL, RH);
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break;
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}
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Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
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Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
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}
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void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
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void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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SDValue &Hi) {
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// Get the dest types - they may not match the input types, e.g. int_to_fp.
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// Get the dest types - they may not match the input types, e.g. int_to_fp.
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@ -889,41 +925,6 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
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}
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}
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}
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}
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void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
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MVT LoVT, HiVT;
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DebugLoc DL = N->getDebugLoc();
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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// Split the input.
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MVT InVT = N->getOperand(0).getValueType();
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SDValue LL, LH, RL, RH;
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switch (getTypeAction(InVT)) {
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default: assert(0 && "Unexpected type action!");
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case WidenVector: assert(0 && "Unimp");
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case Legal: {
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assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
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MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
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LoVT.getVectorNumElements());
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LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
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DAG.getIntPtrConstant(0));
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LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
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DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
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RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
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DAG.getIntPtrConstant(0));
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RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
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DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
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break;
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}
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case SplitVector:
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GetSplitVector(N->getOperand(0), LL, LH);
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GetSplitVector(N->getOperand(1), RL, RH);
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break;
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}
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Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
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Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand Vector Splitting
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// Operand Vector Splitting
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@ -1149,7 +1150,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
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case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
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case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
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case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
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case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
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case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
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case ISD::VECTOR_SHUFFLE:
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case ISD::VECTOR_SHUFFLE:
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Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
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Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
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break;
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break;
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case ISD::VSETCC:
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case ISD::VSETCC:
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@ -1464,7 +1465,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
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MaskOps[i] = i;
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MaskOps[i] = i;
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MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
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MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
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}
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}
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return DAG.getVectorShuffle(WidenVT, dl,
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return DAG.getVectorShuffle(WidenVT, dl,
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GetWidenedVector(N->getOperand(0)),
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GetWidenedVector(N->getOperand(0)),
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GetWidenedVector(N->getOperand(1)),
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GetWidenedVector(N->getOperand(1)),
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&MaskOps[0]);
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&MaskOps[0]);
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