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https://github.com/RPCS3/llvm-mirror.git
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Regenerate rotated uxt tests
This commit is contained in:
Simon Pilgrim
parent
0f06c0a955
commit
f3d8f34048
@ -1,18 +1,21 @@
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; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefix=CHECK-V6
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; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s --check-prefix=CHECK-V7
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6 | FileCheck %s --check-prefixes=CHECK,CHECK-V6
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+v7 | FileCheck %s --check-prefixes=CHECK,CHECK-V7
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define zeroext i8 @test1(i32 %A.u) {
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; CHECK-LABEL: test1
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; CHECK-V6: uxtb
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; CHECK-V7: uxtb
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb r0, r0
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; CHECK-NEXT: bx lr
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%B.u = trunc i32 %A.u to i8
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ret i8 %B.u
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}
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define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
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; CHECK-LABEL: test2
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; CHECK-V6: uxtab r0, r0, r1
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; CHECK-V7: uxtab r0, r0, r1
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; CHECK-LABEL: test2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtab r0, r0, r1
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; CHECK-NEXT: bx lr
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%C.u = trunc i32 %B.u to i8
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%D.u = zext i8 %C.u to i32
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%E.u = add i32 %A.u, %D.u
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@ -20,9 +23,16 @@ define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
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}
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define zeroext i32 @test3(i32 %A.u) {
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; CHECK-LABEL: test3
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; CHECK-V6-NOT: ubfx
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; CHECK-V7: ubfx r0, r0, #8, #16
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; CHECK-V6-LABEL: test3:
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; CHECK-V6: @ %bb.0:
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; CHECK-V6-NEXT: lsr r0, r0, #8
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; CHECK-V6-NEXT: uxth r0, r0
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; CHECK-V6-NEXT: bx lr
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;
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; CHECK-V7-LABEL: test3:
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; CHECK-V7: @ %bb.0:
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; CHECK-V7-NEXT: ubfx r0, r0, #8, #16
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; CHECK-V7-NEXT: bx lr
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%B.u = lshr i32 %A.u, 8
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%C.u = shl i32 %A.u, 24
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%D.u = or i32 %B.u, %C.u
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@ -32,9 +42,16 @@ define zeroext i32 @test3(i32 %A.u) {
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}
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define zeroext i32 @test4(i32 %A.u) {
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; CHECK-LABEL: test4
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; CHECK-V6-NOT: ubfx
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; CHECK-V7: ubfx r0, r0, #8, #8
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; CHECK-V6-LABEL: test4:
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; CHECK-V6: @ %bb.0:
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; CHECK-V6-NEXT: lsr r0, r0, #8
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; CHECK-V6-NEXT: uxtb r0, r0
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; CHECK-V6-NEXT: bx lr
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;
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; CHECK-V7-LABEL: test4:
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; CHECK-V7: @ %bb.0:
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; CHECK-V7-NEXT: ubfx r0, r0, #8, #8
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; CHECK-V7-NEXT: bx lr
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%B.u = lshr i32 %A.u, 8
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%C.u = shl i32 %A.u, 24
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%D.u = or i32 %B.u, %C.u
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@ -44,17 +61,19 @@ define zeroext i32 @test4(i32 %A.u) {
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}
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define zeroext i16 @test5(i32 %A.u) {
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; CHECK-LABEL: test5
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; CHECK-V6: uxth
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; CHECK-V7: uxth
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; CHECK-LABEL: test5:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxth r0, r0
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; CHECK-NEXT: bx lr
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%B.u = trunc i32 %A.u to i16
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ret i16 %B.u
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}
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define zeroext i32 @test6(i32 %A.u, i32 %B.u) {
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; CHECK-LABEL: test6
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; CHECK-V6: uxtah r0, r0, r1
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; CHECK-V7: uxtah r0, r0, r1
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; CHECK-LABEL: test6:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtah r0, r0, r1
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; CHECK-NEXT: bx lr
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%C.u = trunc i32 %B.u to i16
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%D.u = zext i16 %C.u to i32
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%E.u = add i32 %A.u, %D.u
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@ -62,9 +81,10 @@ define zeroext i32 @test6(i32 %A.u, i32 %B.u) {
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}
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define zeroext i32 @test7(i32 %A, i32 %X) {
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; CHECK-LABEL: test7
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; CHECK-V6: uxtab r0, r1, r0, ror #8
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; CHECK-V7: uxtab r0, r1, r0, ror #8
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; CHECK-LABEL: test7:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtab r0, r1, r0, ror #8
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; CHECK-NEXT: bx lr
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%B = lshr i32 %A, 8
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%C = shl i32 %A, 24
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%D = or i32 %B, %C
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@ -75,9 +95,10 @@ define zeroext i32 @test7(i32 %A, i32 %X) {
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}
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define zeroext i32 @test8(i32 %A, i32 %X) {
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; CHECK-LABEL: test8
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; CHECK-V6: uxtab r0, r1, r0, ror #16
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; CHECK-V7: uxtab r0, r1, r0, ror #16
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; CHECK-LABEL: test8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtab r0, r1, r0, ror #16
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; CHECK-NEXT: bx lr
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%B = lshr i32 %A, 16
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%C = shl i32 %A, 16
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%D = or i32 %B, %C
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@ -88,9 +109,10 @@ define zeroext i32 @test8(i32 %A, i32 %X) {
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}
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define zeroext i32 @test9(i32 %A, i32 %X) {
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; CHECK-LABEL: test9
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; CHECK-V6: uxtah r0, r1, r0, ror #8
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; CHECK-V7: uxtah r0, r1, r0, ror #8
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; CHECK-LABEL: test9:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtah r0, r1, r0, ror #8
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; CHECK-NEXT: bx lr
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%B = lshr i32 %A, 8
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%C = shl i32 %A, 24
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%D = or i32 %B, %C
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@ -101,9 +123,10 @@ define zeroext i32 @test9(i32 %A, i32 %X) {
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}
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define zeroext i32 @test10(i32 %A, i32 %X) {
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; CHECK-LABEL: test10
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; CHECK-V6: uxtah r0, r1, r0, ror #24
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; CHECK-V7: uxtah r0, r1, r0, ror #24
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; CHECK-LABEL: test10:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtah r0, r1, r0, ror #24
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; CHECK-NEXT: bx lr
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%B = lshr i32 %A, 24
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%C = shl i32 %A, 8
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%D = or i32 %B, %C
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@ -114,18 +137,20 @@ define zeroext i32 @test10(i32 %A, i32 %X) {
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}
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define zeroext i32 @test11(i32 %A, i32 %X) {
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; CHECK-LABEL: test11
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; CHECK-V6: uxtab r0, r1, r0
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; CHECK-V7: uxtab r0, r1, r0
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; CHECK-LABEL: test11:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtab r0, r1, r0
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; CHECK-NEXT: bx lr
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%B = and i32 %A, 255
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%add = add i32 %X, %B
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ret i32 %add
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}
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define zeroext i32 @test12(i32 %A, i32 %X) {
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; CHECK-LABEL: test12
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; CHECK-V6: uxtab r0, r1, r0, ror #8
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; CHECK-V7: uxtab r0, r1, r0, ror #8
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; CHECK-LABEL: test12:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtab r0, r1, r0, ror #8
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; CHECK-NEXT: bx lr
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%B = lshr i32 %A, 8
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%and = and i32 %B, 255
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%add = add i32 %and, %X
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@ -133,9 +158,10 @@ define zeroext i32 @test12(i32 %A, i32 %X) {
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}
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define zeroext i32 @test13(i32 %A, i32 %X) {
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; CHECK-LABEL: test13
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; CHECK-V6: uxtab r0, r1, r0, ror #16
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; CHECK-V7: uxtab r0, r1, r0, ror #16
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; CHECK-LABEL: test13:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtab r0, r1, r0, ror #16
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; CHECK-NEXT: bx lr
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%B = lshr i32 %A, 16
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%and = and i32 %B, 255
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%add = add i32 %and, %X
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@ -143,18 +169,20 @@ define zeroext i32 @test13(i32 %A, i32 %X) {
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}
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define zeroext i32 @test14(i32 %A, i32 %X) {
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; CHECK-LABEL: test14
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; CHECK-V6: uxtah r0, r1, r0
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; CHECK-V7: uxtah r0, r1, r0
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; CHECK-LABEL: test14:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtah r0, r1, r0
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; CHECK-NEXT: bx lr
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%B = and i32 %A, 65535
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%add = add i32 %X, %B
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ret i32 %add
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}
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define zeroext i32 @test15(i32 %A, i32 %X) {
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; CHECK-LABEL: test15
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; CHECK-V6: uxtah r0, r1, r0, ror #8
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; CHECK-V7: uxtah r0, r1, r0, ror #8
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; CHECK-LABEL: test15:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtah r0, r1, r0, ror #8
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; CHECK-NEXT: bx lr
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%B = lshr i32 %A, 8
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%and = and i32 %B, 65535
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%add = add i32 %and, %X
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@ -162,9 +190,10 @@ define zeroext i32 @test15(i32 %A, i32 %X) {
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}
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define zeroext i32 @test16(i32 %A, i32 %X) {
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; CHECK-LABEL: test16
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; CHECK-V6: uxtah r0, r1, r0, ror #24
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; CHECK-V7: uxtah r0, r1, r0, ror #24
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; CHECK-LABEL: test16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtah r0, r1, r0, ror #24
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; CHECK-NEXT: bx lr
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%B = lshr i32 %A, 24
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%C = shl i32 %A, 8
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%D = or i32 %B, %C
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