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[PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled

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Summary:
In https://bugs.llvm.org/show_bug.cgi?id=45297, it fails selecting
instructions for `PPCISD::ST_VSR_SCAL_INT`. The reason it generate the
`PPCISD::ST_VSR_SCAL_INT` with `-power8-vector` in IR is PPC's
combiner checks `hasP8Altivec` rather than `hasP8Vector`. This patch
should resolve PR45297.

Differential Revision: https://reviews.llvm.org/D76773
This commit is contained in:
Kai Luo 2020-04-01 02:15:25 +00:00
parent 471fb1a342
commit f3da7ee9fe
2 changed files with 12 additions and 3 deletions
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2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -13768,7 +13768,7 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
(Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
(Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Altivec() ||
if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)
return SDValue();

13
test/CodeGen/PowerPC/pr45297.ll
View File

@ -1,11 +1,20 @@
; RUN: not --crash llc -verify-machineinstrs \
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
; RUN: -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Cannot select: {{.*}}: ch = PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>
@Global = dso_local global i32 55, align 4
define dso_local void @test(float %0) local_unnamed_addr {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fctiwz f0, f1
; CHECK-NEXT: addi r3, r1, -4
; CHECK-NEXT: addis r4, r2, Global@toc@ha
; CHECK-NEXT: stfiwx f0, 0, r3
; CHECK-NEXT: lwz r3, -4(r1)
; CHECK-NEXT: stw r3, Global@toc@l(r4)
; CHECK-NEXT: blr
entry:
%1 = fptosi float %0 to i32
store i32 %1, i32* @Global, align 4