mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 19:12:56 +02:00
[AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones.
llvm-svn: 270317
This commit is contained in:
Craig Topper
parent
30a8fe51db
commit
f3e023e70e
@ -625,11 +625,15 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
|
||||
break;
|
||||
|
||||
case X86::VPERMQYri:
|
||||
case X86::VPERMQZ256ri:
|
||||
case X86::VPERMPDYri:
|
||||
case X86::VPERMPDZ256ri:
|
||||
Src1Name = getRegName(MI->getOperand(1).getReg());
|
||||
// FALL THROUGH.
|
||||
case X86::VPERMQYmi:
|
||||
case X86::VPERMQZ256mi:
|
||||
case X86::VPERMPDYmi:
|
||||
case X86::VPERMPDZ256mi:
|
||||
if (MI->getOperand(NumOperands - 1).isImm())
|
||||
DecodeVPERMMask(MI->getOperand(NumOperands - 1).getImm(),
|
||||
ShuffleMask);
|
||||
|
||||
@ -8463,21 +8463,23 @@ let Predicates = [HasAVX, NoVLX], AddedComplexity = 20 in {
|
||||
|
||||
multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
|
||||
ValueType OpVT, X86FoldableSchedWrite Sched> {
|
||||
def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set VR256:$dst,
|
||||
(OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
|
||||
Sched<[Sched]>, VEX_4V, VEX_L;
|
||||
def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
|
||||
(ins VR256:$src1, i256mem:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set VR256:$dst,
|
||||
(OpVT (X86VPermv VR256:$src1,
|
||||
(bitconvert (mem_frag addr:$src2)))))]>,
|
||||
Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
|
||||
let Predicates = [HasAVX2, NoVLX] in {
|
||||
def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set VR256:$dst,
|
||||
(OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
|
||||
Sched<[Sched]>, VEX_4V, VEX_L;
|
||||
def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
|
||||
(ins VR256:$src1, i256mem:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set VR256:$dst,
|
||||
(OpVT (X86VPermv VR256:$src1,
|
||||
(bitconvert (mem_frag addr:$src2)))))]>,
|
||||
Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
|
||||
}
|
||||
}
|
||||
|
||||
defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
|
||||
@ -8486,21 +8488,23 @@ defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
|
||||
|
||||
multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
|
||||
ValueType OpVT, X86FoldableSchedWrite Sched> {
|
||||
def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
|
||||
(ins VR256:$src1, u8imm:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set VR256:$dst,
|
||||
(OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
|
||||
Sched<[Sched]>, VEX, VEX_L;
|
||||
def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
|
||||
(ins i256mem:$src1, u8imm:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set VR256:$dst,
|
||||
(OpVT (X86VPermi (mem_frag addr:$src1),
|
||||
(i8 imm:$src2))))]>,
|
||||
Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
|
||||
let Predicates = [HasAVX2, NoVLX] in {
|
||||
def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
|
||||
(ins VR256:$src1, u8imm:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set VR256:$dst,
|
||||
(OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
|
||||
Sched<[Sched]>, VEX, VEX_L;
|
||||
def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
|
||||
(ins i256mem:$src1, u8imm:$src2),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
[(set VR256:$dst,
|
||||
(OpVT (X86VPermi (mem_frag addr:$src1),
|
||||
(i8 imm:$src2))))]>,
|
||||
Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
|
||||
}
|
||||
}
|
||||
|
||||
defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
|
||||
|
||||
@ -9170,7 +9170,7 @@ define <4 x double>@test_int_x86_avx512_mask_perm_df_256(<4 x double> %x0, i32 %
|
||||
; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
|
||||
; CHECK-NEXT: vpermpd $3, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0xfd,0x29,0x01,0xc8,0x03]
|
||||
; CHECK-NEXT: vpermpd $3, %ymm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf3,0xfd,0xa9,0x01,0xd0,0x03]
|
||||
; CHECK-NEXT: vpermpd $3, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0xfd,0x01,0xc0,0x03]
|
||||
; CHECK-NEXT: vpermpd $3, %ymm0, %ymm0 ## encoding: [0x62,0xf3,0xfd,0x28,0x01,0xc0,0x03]
|
||||
; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0]
|
||||
; CHECK-NEXT: vaddpd %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0xf5,0x28,0x58,0xca]
|
||||
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0 ## encoding: [0x62,0xf1,0xf5,0x28,0x58,0xc0]
|
||||
@ -9191,7 +9191,7 @@ define <4 x i64>@test_int_x86_avx512_mask_perm_di_256(<4 x i64> %x0, i32 %x1, <4
|
||||
; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
|
||||
; CHECK-NEXT: vpermq $3, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0xfd,0x29,0x00,0xc8,0x03]
|
||||
; CHECK-NEXT: vpermq $3, %ymm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf3,0xfd,0xa9,0x00,0xd0,0x03]
|
||||
; CHECK-NEXT: vpermq $3, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0xfd,0x00,0xc0,0x03]
|
||||
; CHECK-NEXT: vpermq $3, %ymm0, %ymm0 ## encoding: [0x62,0xf3,0xfd,0x28,0x00,0xc0,0x03]
|
||||
; CHECK-NEXT: ## ymm0 = ymm0[3,0,0,0]
|
||||
; CHECK-NEXT: vpaddq %ymm2, %ymm1, %ymm1 ## encoding: [0x62,0xf1,0xf5,0x28,0xd4,0xca]
|
||||
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ## encoding: [0x62,0xf1,0xf5,0x28,0xd4,0xc0]
|
||||
@ -9251,7 +9251,7 @@ define <8 x float>@test_int_x86_avx512_mask_permvar_sf_256(<8 x float> %x0, <8 x
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf2,0x7d,0x29,0x16,0xd1]
|
||||
; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm3 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xa9,0x16,0xd9]
|
||||
; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x16,0xc1]
|
||||
; CHECK-NEXT: vpermps %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf2,0x7d,0x28,0x16,0xc1]
|
||||
; CHECK-NEXT: vaddps %ymm3, %ymm2, %ymm1 ## encoding: [0x62,0xf1,0x6c,0x28,0x58,0xcb]
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ## encoding: [0x62,0xf1,0x74,0x28,0x58,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
@ -9271,7 +9271,7 @@ define <8 x i32>@test_int_x86_avx512_mask_permvar_si_256(<8 x i32> %x0, <8 x i32
|
||||
; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
|
||||
; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf2,0x7d,0x29,0x36,0xd1]
|
||||
; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm3 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xa9,0x36,0xd9]
|
||||
; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x36,0xc1]
|
||||
; CHECK-NEXT: vpermd %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf2,0x7d,0x28,0x36,0xc1]
|
||||
; CHECK-NEXT: vpaddd %ymm3, %ymm2, %ymm1 ## encoding: [0x62,0xf1,0x6d,0x28,0xfe,0xcb]
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ## encoding: [0x62,0xf1,0x75,0x28,0xfe,0xc0]
|
||||
; CHECK-NEXT: retq ## encoding: [0xc3]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user