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[Target] Use llvm::append_range (NFC)

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This commit is contained in:
Kazu Hirata 2021-01-23 10:56:31 -08:00
parent f4934140cd
commit f3e18e1dd6
12 changed files with 22 additions and 44 deletions
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3
lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp
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@ -81,8 +81,7 @@ recursivelyVisitUsers(GlobalValue &GV,
continue;
}
for (User *UU : U->users())
Stack.push_back(UU);
append_range(Stack, U->users());
}
}

8
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -6208,12 +6208,10 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
SmallVector<SDValue, 26> Ops;
if (BaseOpcode->Store || BaseOpcode->Atomic)
Ops.push_back(VData); // vdata
if (UseNSA) {
for (const SDValue &Addr : VAddrs)
Ops.push_back(Addr);
} else {
if (UseNSA)
append_range(Ops, VAddrs);
else
Ops.push_back(VAddr);
}
Ops.push_back(Op.getOperand(ArgOffset + Intr->RsrcIndex));
if (BaseOpcode->Sampler)
Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex));

9
lib/Target/AMDGPU/SILowerI1Copies.cpp
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@ -177,10 +177,8 @@ public:
}
}
if (Divergent && PDT.dominates(&DefBlock, MBB)) {
for (MachineBasicBlock *Succ : MBB->successors())
Stack.push_back(Succ);
}
if (Divergent && PDT.dominates(&DefBlock, MBB))
append_range(Stack, MBB->successors());
}
while (!Stack.empty()) {
@ -189,8 +187,7 @@ public:
continue;
ReachableOrdered.push_back(MBB);
for (MachineBasicBlock *Succ : MBB->successors())
Stack.push_back(Succ);
append_range(Stack, MBB->successors());
}
for (MachineBasicBlock *MBB : ReachableOrdered) {

9
lib/Target/ARM/ARMISelLowering.cpp
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@ -3556,8 +3556,7 @@ static bool allUsersAreInFunction(const Value *V, const Function *F) {
while (!Worklist.empty()) {
auto *U = Worklist.pop_back_val();
if (isa<ConstantExpr>(U)) {
for (auto *UU : U->users())
Worklist.push_back(UU);
append_range(Worklist, U->users());
continue;
}
@ -19126,8 +19125,7 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
SmallVector<Value *, 6> Ops;
Ops.push_back(Builder.CreateBitCast(BaseAddr, Int8Ptr));
for (auto S : Shuffles)
Ops.push_back(S);
append_range(Ops, Shuffles);
Ops.push_back(Builder.getInt32(SI->getAlignment()));
Builder.CreateCall(VstNFunc, Ops);
} else {
@ -19143,8 +19141,7 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
SmallVector<Value *, 6> Ops;
Ops.push_back(Builder.CreateBitCast(BaseAddr, EltPtrTy));
for (auto S : Shuffles)
Ops.push_back(S);
append_range(Ops, Shuffles);
for (unsigned F = 0; F < Factor; F++) {
Ops.push_back(Builder.getInt32(F));
Builder.CreateCall(VstNFunc, Ops);

3
lib/Target/ARM/ARMLowOverheadLoops.cpp
View File

@ -143,8 +143,7 @@ namespace {
// Insert exit blocks.
SmallVector<MachineBasicBlock*, 2> ExitBlocks;
ML.getExitBlocks(ExitBlocks);
for (auto *MBB : ExitBlocks)
Order.push_back(MBB);
append_range(Order, ExitBlocks);
// Then add the loop body.
Search(ML.getHeader());

3
lib/Target/ARM/ARMParallelDSP.cpp
View File

@ -202,8 +202,7 @@ namespace {
public:
WidenedLoad(SmallVectorImpl<LoadInst*> &Lds, LoadInst *Wide)
: NewLd(Wide) {
for (auto *I : Lds)
Loads.push_back(I);
append_range(Loads, Lds);
}
LoadInst *getLoad() {
return NewLd;

3
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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@ -315,8 +315,7 @@ HexagonTargetLowering::getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
const SDLoc &dl, SelectionDAG &DAG) const {
SmallVector<SDValue,4> IntOps;
IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32));
for (const SDValue &Op : Ops)
IntOps.push_back(Op);
append_range(IntOps, Ops);
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps);
}

9
lib/Target/Hexagon/HexagonSplitDouble.cpp
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@ -574,12 +574,9 @@ void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
LoopVector WorkQ;
for (auto I : *MLI)
WorkQ.push_back(I);
for (unsigned i = 0; i < WorkQ.size(); ++i) {
for (auto I : *WorkQ[i])
WorkQ.push_back(I);
}
append_range(WorkQ, *MLI);
for (unsigned i = 0; i < WorkQ.size(); ++i)
append_range(WorkQ, *WorkQ[i]);
USet Rs;
for (unsigned i = 0, n = WorkQ.size(); i < n; ++i) {

3
lib/Target/Hexagon/RDFDeadCode.cpp
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@ -195,8 +195,7 @@ bool DeadCodeElimination::erase(const SetVector<NodeId> &Nodes) {
// If it's a code node, add all ref nodes from it.
uint16_t Kind = BA.Addr->getKind();
if (Kind == NodeAttrs::Stmt || Kind == NodeAttrs::Phi) {
for (auto N : NodeAddr<CodeNode*>(BA).Addr->members(DFG))
DRNs.push_back(N);
append_range(DRNs, NodeAddr<CodeNode*>(BA).Addr->members(DFG));
DINs.push_back(DFG.addr<InstrNode*>(I));
} else {
llvm_unreachable("Unexpected code node");

4
lib/Target/PowerPC/PPCCTRLoops.cpp
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@ -148,9 +148,7 @@ queue_preds:
return false;
}
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
PIE = MBB->pred_end(); PI != PIE; ++PI)
Preds.push_back(*PI);
append_range(Preds, MBB->predecessors());
}
do {

9
lib/Target/X86/X86PartialReduction.cpp
View File

@ -392,8 +392,7 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
break;
// Push incoming values to the worklist.
for (Value *InV : PN->incoming_values())
Worklist.push_back(InV);
append_range(Worklist, PN->incoming_values());
continue;
}
@ -402,8 +401,7 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
if (BO->getOpcode() == Instruction::Add) {
// Simple case. Single use, just push its operands to the worklist.
if (BO->hasNUses(BO == Root ? 2 : 1)) {
for (Value *Op : BO->operands())
Worklist.push_back(Op);
append_range(Worklist, BO->operands());
continue;
}
@ -426,8 +424,7 @@ static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) {
continue;
// The phi forms a loop with this Add, push its operands.
for (Value *Op : BO->operands())
Worklist.push_back(Op);
append_range(Worklist, BO->operands());
}
}
}

3
lib/Target/X86/X86WinEHState.cpp
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@ -704,8 +704,7 @@ void WinEHStatePass::addStateStores(Function &F, WinEHFuncInfo &FuncInfo) {
// enqueue it's successors to see if we can infer their states.
InitialStates.insert({BB, PredState});
FinalStates.insert({BB, PredState});
for (BasicBlock *SuccBB : successors(BB))
Worklist.push_back(SuccBB);
append_range(Worklist, successors(BB));
}
// Try to hoist stores from successors.