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Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
llvm-svn: 106368
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@ -1389,7 +1389,6 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const {
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SelectionDAG& DAG) const {
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const Function *CallerF = DAG.getMachineFunction().getFunction();
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const Function *CallerF = DAG.getMachineFunction().getFunction();
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CallingConv::ID CallerCC = CallerF->getCallingConv();
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CallingConv::ID CallerCC = CallerF->getCallingConv();
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bool CCMatch = CallerCC == CalleeCC;
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bool CCMatch = CallerCC == CalleeCC;
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@ -1407,19 +1406,29 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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if (isCalleeStructRet || isCallerStructRet)
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if (isCalleeStructRet || isCallerStructRet)
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return false;
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return false;
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// FIXME: Completely disable sibcal for Thumb1 since Thumb1RegisterInfo::
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// emitEpilogue is not ready for them.
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if (Subtarget->isThumb1Only())
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return false;
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if (isa<ExternalSymbolSDNode>(Callee))
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return false;
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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if (Subtarget->isThumb1Only())
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return false;
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// On Thumb, for the moment, we can only do this to functions defined in this
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// On Thumb, for the moment, we can only do this to functions defined in this
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// compilation, or to indirect calls. A Thumb B to an ARM function is not
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// compilation, or to indirect calls. A Thumb B to an ARM function is not
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// easily fixed up in the linker, unlike BL.
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// easily fixed up in the linker, unlike BL.
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if (Subtarget->isThumb()) {
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if (Subtarget->isThumb()) {
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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const GlobalValue *GV = G->getGlobal();
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const GlobalValue *GV = G->getGlobal();
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if (GV->isDeclaration() || GV->isWeakForLinker())
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if (GV->isDeclaration() || GV->isWeakForLinker())
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return false;
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return false;
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} else if (isa<ExternalSymbolSDNode>(Callee)) {
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return false;
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}
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}
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}
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}
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// If the calling conventions do not match, then we'd better make sure the
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// If the calling conventions do not match, then we'd better make sure the
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// results are returned in the same way as what the caller expects.
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// results are returned in the same way as what the caller expects.
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if (!CCMatch) {
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if (!CCMatch) {
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@ -7,22 +7,25 @@
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declare void @g(i32, i32, i32, i32)
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declare void @g(i32, i32, i32, i32)
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define void @f() {
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define void @t1() {
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; CHECKELF: t1:
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; CHECKELF: PLT
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; CHECKELF: PLT
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call void @g( i32 1, i32 2, i32 3, i32 4 )
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call void @g( i32 1, i32 2, i32 3, i32 4 )
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ret void
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ret void
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}
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}
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define void @g.upgrd.1() {
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define void @t2() {
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; CHECKV4: t2:
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; CHECKV4: bx r0 @ TAILCALL
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; CHECKV4: bx r0 @ TAILCALL
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; CHECKV5: t2:
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; CHECKV5: bx r0 @ TAILCALL
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; CHECKV5: bx r0 @ TAILCALL
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%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
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%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
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%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
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%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
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ret void
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ret void
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}
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}
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define i32* @m_231b(i32, i32, i32*, i32*, i32*) nounwind {
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define i32* @t3(i32, i32, i32*, i32*, i32*) nounwind {
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; CHECKV4: m_231b
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; CHECKV4: t3:
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; CHECKV4: bx r{{.*}}
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; CHECKV4: bx r{{.*}}
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BB0:
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BB0:
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%5 = inttoptr i32 %0 to i32* ; <i32*> [#uses=1]
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%5 = inttoptr i32 %0 to i32* ; <i32*> [#uses=1]
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8
test/CodeGen/Thumb/2010-06-18-SibCallCrash.ll
Normal file
8
test/CodeGen/Thumb/2010-06-18-SibCallCrash.ll
Normal file
@ -0,0 +1,8 @@
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; RUN: llc -march=thumb < %s
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; rdar://8104457
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define arm_apcscc void @t(i32* %m) nounwind {
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entry:
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tail call arm_apcscc void undef(i32* %m, i16 zeroext undef) nounwind
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ret void
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}
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@ -11,7 +11,7 @@ define void @f() {
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; LINUX: f:
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; LINUX: f:
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; LINUX: bl g
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; LINUX: bl g
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call void @g( i32 1, i32 2, i32 3, i32 4 )
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tail call void @g( i32 1, i32 2, i32 3, i32 4 )
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ret void
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ret void
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}
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}
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