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[ARM] Regenerate tests. NFC
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@ -1803,7 +1803,7 @@ define arm_aapcs_vfpcc float @half_short_mac(half* nocapture readonly %a, i16* n
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; CHECK-NEXT: adds r2, r0, #4
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB11_5: @ %for.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrsh.w r4, [r3, #2]
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; CHECK-NEXT: vldr.16 s2, [r2, #2]
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; CHECK-NEXT: add.w r12, r12, #4
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@ -377,24 +377,24 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_char(i8* nocapture readonly
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; CHECK-NEXT: cmp r6, r1
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; CHECK-NEXT: add.w r5, r0, r12
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; CHECK-NEXT: cset lr, hi
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; CHECK-NEXT: cmp r4, r3
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; CHECK-NEXT: cmp r4, r3
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; CHECK-NEXT: cset r4, hi
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; CHECK-NEXT: cmp r6, r0
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; CHECK-NEXT: cmp r6, r0
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; CHECK-NEXT: cset r6, hi
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; CHECK-NEXT: cmp r5, r3
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; CHECK-NEXT: cmp r5, r3
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; CHECK-NEXT: cset r5, hi
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; CHECK-NEXT: ands r5, r6
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; CHECK-NEXT: movs r6, #1
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; CHECK-NEXT: lsls r5, r5, #31
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: itt eq
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; CHECK-NEXT: andeq.w r5, r4, lr
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; CHECK-NEXT: lslseq.w r5, r5, #31
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; CHECK-NEXT: beq .LBB5_4
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; CHECK-NEXT: beq .LBB5_4
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; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
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; CHECK-NEXT: sub.w r5, r12, #1
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; CHECK-NEXT: and r9, r12, #3
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; CHECK-NEXT: cmp r5, #3
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; CHECK-NEXT: bhs .LBB5_6
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; CHECK-NEXT: sub.w r5, r12, #1
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; CHECK-NEXT: and r9, r12, #3
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; CHECK-NEXT: cmp r5, #3
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; CHECK-NEXT: bhs .LBB5_6
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; CHECK-NEXT: @ %bb.3:
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: b .LBB5_8
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@ -418,28 +418,28 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_char(i8* nocapture readonly
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; CHECK-NEXT: adds r6, r1, #1
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB5_7: @ %for.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrb r8, [r5, #-3]
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; CHECK-NEXT: add.w r12, r12, #4
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; CHECK-NEXT: ldrb r7, [r6, #-1]
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; CHECK-NEXT: smlabb r7, r7, r8, r2
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; CHECK-NEXT: str r7, [r4, #-8]
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; CHECK-NEXT: ldrb r8, [r5, #-2]
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; CHECK-NEXT: ldrb r7, [r6]
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; CHECK-NEXT: smlabb r7, r7, r8, r2
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; CHECK-NEXT: str r7, [r4, #-4]
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; CHECK-NEXT: ldrb r8, [r5, #-1]
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; CHECK-NEXT: ldrb r7, [r6, #1]
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; CHECK-NEXT: smlabb r7, r7, r8, r2
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; CHECK-NEXT: str r7, [r4]
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; CHECK-NEXT: ldrb.w r8, [r5]
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; CHECK-NEXT: adds r5, #4
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; CHECK-NEXT: ldrb r7, [r6, #2]
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; CHECK-NEXT: adds r6, #4
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; CHECK-NEXT: smlabb r7, r7, r8, r2
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; CHECK-NEXT: str r7, [r4, #4]
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; CHECK-NEXT: adds r4, #16
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; CHECK-NEXT: le lr, .LBB5_7
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrb r8, [r5, #-3]
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; CHECK-NEXT: add.w r12, r12, #4
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; CHECK-NEXT: ldrb r7, [r6, #-1]
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; CHECK-NEXT: smlabb r7, r7, r8, r2
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; CHECK-NEXT: str r7, [r4, #-8]
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; CHECK-NEXT: ldrb r8, [r5, #-2]
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; CHECK-NEXT: ldrb r7, [r6]
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; CHECK-NEXT: smlabb r7, r7, r8, r2
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; CHECK-NEXT: str r7, [r4, #-4]
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; CHECK-NEXT: ldrb r8, [r5, #-1]
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; CHECK-NEXT: ldrb r7, [r6, #1]
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; CHECK-NEXT: smlabb r7, r7, r8, r2
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; CHECK-NEXT: str r7, [r4]
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; CHECK-NEXT: ldrb.w r8, [r5]
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; CHECK-NEXT: adds r5, #4
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; CHECK-NEXT: ldrb r7, [r6, #2]
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; CHECK-NEXT: adds r6, #4
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; CHECK-NEXT: smlabb r7, r7, r8, r2
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; CHECK-NEXT: str r7, [r4, #4]
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; CHECK-NEXT: adds r4, #16
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; CHECK-NEXT: le lr, .LBB5_7
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; CHECK-NEXT: .LBB5_8: @ %for.cond.cleanup.loopexit.unr-lcssa
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; CHECK-NEXT: wls lr, r9, .LBB5_11
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; CHECK-NEXT: @ %bb.9: @ %for.body.epil.preheader
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: opt -instcombine %s | llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - | FileCheck %s
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declare <16 x i1> @llvm.arm.mve.vctp8(i32)
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: opt -instcombine -S %s | FileCheck --check-prefix=IR %s
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; RUN: opt -instcombine %s | llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -O3 -o - | FileCheck --check-prefix=ASM %s
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