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AMDGPU: v_cndmask_b32 does not def vcc

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Fixes verifier errors after SIShrinkInstructions.

llvm-svn: 272351
This commit is contained in:
Matt Arsenault 2016-06-10 00:18:41 +00:00
parent 7240ff2203
commit f4490b9ad5
2 changed files with 29 additions and 2 deletions
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4
lib/Target/AMDGPU/SIInstrInfo.td
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@ -2116,8 +2116,8 @@ multiclass VOP2e_Helper <vop2 op, string opName, VOPProfile p,
list<dag> pat32, list<dag> pat64, list<dag> pat32, list<dag> pat64,
string revOp, bit useSGPRInput> { string revOp, bit useSGPRInput> {
let SchedRW = [Write32Bit, WriteSALU] in { let SchedRW = [Write32Bit] in {
let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in { let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
defm _e32 : VOP2_m <op, opName, p, pat32, revOp>; defm _e32 : VOP2_m <op, opName, p, pat32, revOp>;
} }

27
test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll Normal file
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@ -0,0 +1,27 @@
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Produces error after adding an implicit deff to v_cndmask_b32
; GCN-LABEL: {{^}}vcc_shrink_vcc_def:
; GCN: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}}
; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
; GCN: v_cndmask_b32_e64 v1, 0, 1, s{{\[[0-9]+:[0-9]+\]}}
define void @vcc_shrink_vcc_def(float %arg, i32 %arg1, float %arg2, i32 %arg3) {
bb0:
%tmp = icmp sgt i32 %arg1, 4
%c = icmp eq i32 %arg3, 0
%tmp4 = select i1 %c, float %arg, float 1.000000e+00
%tmp5 = fcmp ogt float %arg2, 0.000000e+00
%tmp6 = fcmp olt float %arg2, 1.000000e+00
%tmp7 = fcmp olt float %arg, %tmp4
%tmp8 = and i1 %tmp5, %tmp6
%tmp9 = and i1 %tmp8, %tmp7
br i1 %tmp9, label %bb1, label %bb2
bb1:
store volatile i32 0, i32 addrspace(1)* undef
br label %bb2
bb2:
ret void
}