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[TableGen] Update xxx-tblgen command document.
Add a few cross-references among TableGen documents. Differential Revision: https://reviews.llvm.org/D90186 Add cross-references between TableGen documents.
This commit is contained in:
Paul C. Anagnostopoulos
parent
fb347a90cf
commit
f49b986f20
@ -1,41 +1,56 @@
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tblgen - Target Description To C++ Code Generator
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=================================================
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xxx-tblgen: Target Description to C++ Code
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==========================================
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.. program:: tblgen
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SYNOPSIS
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--------
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:program:`tblgen` [*options*] [*filename*]
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:program:`xxx-tblgen` [*options*] [*filename*]
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DESCRIPTION
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-----------
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:program:`tblgen` translates from target description (``.td``) files into C++
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code that can be included in the definition of an LLVM target library. Most
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users of LLVM will not need to use this program. It is only for assisting with
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writing an LLVM target backend.
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:program:`xxx-tblgen` is a family of programs that translates target
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description (``.td``) files into C++ code and other output formats. Most
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users of LLVM will not need to use this program. It is used only for
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writing parts of the compiler or LLVM target backends.
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The input and output of :program:`tblgen` is beyond the scope of this short
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introduction; please see the :doc:`introduction to TableGen
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<../TableGen/index>`.
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The details of the input and output of :program:`xxx-tblgen` is beyond the
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scope of this short introduction; please see the :doc:`TableGen Overview
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<../TableGen/index>` for an introduction and for references to additional
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TableGen documents.
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The *filename* argument specifies the name of a Target Description (``.td``)
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file to read as input.
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The *filename* argument specifies the name of the Target Description (``.td``)
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file that TableGen processes.
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OPTIONS
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-------
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.. program:: tblgen
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General Options
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~~~~~~~~~~~~~~~
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.. option:: -help
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Print a summary of command line options.
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.. option:: -o filename
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.. option:: -D=macroname
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Specify the output file name. If ``filename`` is ``-``, then
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:program:`tblgen` sends its output to standard output.
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Specify the name of a macro to be defined. The name is defined, but it
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has no particular value.
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.. option:: -d=filename
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Specify the name of the dependency filename.
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.. option:: --debug
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Enable debug output.
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.. option:: -dump-json
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Print a JSON representation of all records, suitable for further
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automated processing.
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.. option:: -I directory
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@ -43,105 +58,642 @@ OPTIONS
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``directory`` value should be a full or partial path to a directory that
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contains target description files.
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.. option:: -asmparsernum N
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.. option:: -o filename
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Make -gen-asm-parser emit assembly writer number ``N``.
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.. option:: -asmwriternum N
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Make -gen-asm-writer emit assembly writer number ``N``.
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.. option:: -class className
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Print the enumeration list for this class.
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Specify the output file name. If ``filename`` is ``-``, then
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:program:`xxx-tblgen` sends its output to standard output.
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.. option:: -print-records
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Print all records to standard output (default).
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Print all classes and records to standard output (default option).
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.. option:: -dump-json
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.. option:: -print-detailed-records
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Print a JSON representation of all records, suitable for further
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automated processing.
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Print a detailed report of all global variables, classes, and records
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to standard output.
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.. option:: -print-enums
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.. option:: --stats
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Print enumeration values for a class.
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Enable statistics output.
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.. option:: -print-sets
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.. option:: -write-if-changed
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Print expanded sets for testing DAG exprs.
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Write the output file only if it is new or has changed. The default
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is true.
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.. option:: -gen-emitter
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Generate machine code emitter.
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.. option:: -gen-register-info
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Generate registers and register classes info.
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.. option:: -gen-instr-info
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Generate instruction descriptions.
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.. option:: -gen-asm-writer
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Generate the assembly writer.
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.. option:: -gen-disassembler
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Generate disassembler.
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.. option:: -gen-pseudo-lowering
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Generate pseudo instruction lowering.
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.. option:: -gen-dag-isel
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Generate a DAG (Directed Acyclic Graph) instruction selector.
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llvm-tblgen Options
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~~~~~~~~~~~~~~~~~~~
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.. option:: -gen-asm-matcher
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Generate assembly instruction matcher.
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.. option:: -match-prefix=prefix
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Make -gen-asm-matcher match only instructions with the given *prefix*.
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.. option:: -gen-asm-parser
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Generate assembly instruction parser.
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.. option:: -asmparsernum=n
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Make -gen-asm-parser emit assembly parser number *n*.
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.. option:: -gen-asm-writer
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Generate assembly writer.
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.. option:: -asmwriternum=n
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Make -gen-asm-writer emit assembly writer number *n*.
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.. option:: -gen-attrs
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Geneerate attributes.
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.. option:: -gen-automata
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Generate generic automata.
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.. option:: -gen-callingconv
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Generate calling convention descriptions.
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.. option:: -gen-compress-inst-emitter
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Generate RISCV compressed instructions.
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.. option:: -gen-ctags
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Generate ctags-compatible index.
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.. option:: -gen-dag-isel
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Generate a DAG (directed acyclic graph) instruction selector.
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.. option:: -instrument-coverage
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Make -gen-dag-isel generate tables to help identify the patterns matched.
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.. option:: -omit-comments
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Make -gen-dag-isel omit comments. The default is false.
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.. option:: -gen-dfa-packetizer
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Generate DFA Packetizer for VLIW targets.
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.. option:: -gen-directive-decl
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Generate directive related declaration code (header file).
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.. option:: -gen-directive-gen
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Generate directive related implementation code part.
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.. option:: -gen-directive-impl
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Generate directive related implementation code.
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.. option:: -gen-disassembler
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Generate disassembler.
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.. option:: -gen-emitter
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Generate machine code emitter.
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.. option:: -gen-exegesis
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Generate llvm-exegesis tables.
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.. option:: -gen-fast-isel
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Generate a "fast" instruction selector.
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Generate a "fast" instruction selector.
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.. option:: -gen-subtarget
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.. option:: -gen-global-isel
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Generate subtarget enumerations.
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Generate GlobalISel selector.
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.. option:: -gisel-coverage-file=filename
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Specify the file from which to retrieve coverage information.
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.. option:: -instrument-gisel-coverage
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Make -gen-global-isel generate coverage instrumentation.
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.. option:: -optimize-match-table
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Make -gen-global-isel generate an optimized version of the match table.
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.. option:: -warn-on-skipped-patterns
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Make -gen-global-isel explain why a pattern was skipped for inclusion.
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.. option:: -gen-global-isel-combiner
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Generate GlobalISel combiner.
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.. option:: -combiners=list
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Make -gen-global-isel-combiner emit the specified combiners.
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.. option:: -gicombiner-show-expansions
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Make -gen-global-isel-combiner use C++ comments to indicate occurences
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of code expansion.
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.. option:: -gicombiner-stop-after-build
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Make -gen-global-isel-combiner stop processing after building the match tree.
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.. option:: -gicombiner-stop-after-parse
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Make -gen-global-isel-combiner stop processing after parsing rules
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and dump state.
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.. option:: -gen-instr-info
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Generate instruction descriptions.
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.. option:: -gen-instr-docs
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Generate instruction documentation.
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.. option:: -gen-intrinsic-enums
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Generate intrinsic enums.
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.. option:: -intrinsic-prefix=prefix
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Make -gen-intrinsic-enums generate intrinsics with this target *prefix*.
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.. option:: -gen-intrinsic-impl
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Generate intrinsic implementation.
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Generate intrinsic information.
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.. option:: -gen-tgt-intrinsic
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.. option:: -gen-opt-parser-defs
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Generate target intrinsic information.
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Generate options definitions.
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.. option:: -gen-enhanced-disassembly-info
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.. option:: -gen-opt-rst
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Generate enhanced disassembly info.
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Generate option RST.
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.. option:: -gen-exegesis
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.. option:: -gen-pseudo-lowering
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Generate llvm-exegesis tables.
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Generate pseudo instruction lowering.
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.. option:: -gen-register-bank
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Generate register bank descriptions.
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.. option:: -gen-register-info
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Generate registers and register classes info.
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.. option:: -register-info-debug
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Make -gen-register-info dump register information for debugging.
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.. option:: -gen-searchable-tables
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Generate generic searchable tables. See :doc:`TableGen BackEnds <./BackEnds>`
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for a detailed description.
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.. option:: -gen-subtarget
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Generate subtarget enumerations.
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.. option:: -gen-x86-EVEX2VEX-tables
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Generate X86 EVEX to VEX compress tables.
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.. option:: -gen-x86-fold-tables
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Generate X86 fold tables.
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.. option:: -long-string-literals
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When emitting large string tables, prefer string literals over
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comma-separated char literals. This can be a readability and
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compile-time performance win, but upsets some compilers.
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.. option:: -print-enums
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Print enumeration values for a class.
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.. option:: -class=classname
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Make -print-enums print the enumeration list for the specified class.
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.. option:: -print-sets
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Print expanded sets for testing DAG exprs.
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.. option:: -version
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Show the version number of this program.
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Show the version number of the program.
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clang-tblgen Options
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~~~~~~~~~~~~~~~~~~~~
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.. option:: -gen-clang-attr-classes
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Generate Clang attribute clases.
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.. option:: -gen-clang-attr-parser-string-switches
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Generate all parser-related attribute string switches.
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.. option:: -gen-clang-attr-subject-match-rules-parser-string-switches
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Generate all parser-related attribute subject match rule string switches.
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.. option:: -gen-clang-attr-impl
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Generate Clang attribute implementations.
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.. option:: -gen-clang-attr-list"
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Generate a Clang attribute list.
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.. option:: -gen-clang-attr-subject-match-rule-list
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Generate a Clang attribute subject match rule list.
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.. option:: -gen-clang-attr-pch-read
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Generate Clang PCH attribute reader.
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.. option:: -gen-clang-attr-pch-write
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Generate Clang PCH attribute writer.
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.. option:: -gen-clang-attr-has-attribute-impl
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Generate a Clang attribute spelling list.
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.. option:: -gen-clang-attr-spelling-index
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Generate a Clang attribute spelling index.
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.. option:: -gen-clang-attr-ast-visitor
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Generate a recursive AST visitor for Clang attributes.
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.. option:: -gen-clang-attr-template-instantiate
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Generate a Clang template instantiate code.
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.. option:: -gen-clang-attr-parsed-attr-list
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Generate a Clang parsed attribute list.
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.. option:: -gen-clang-attr-parsed-attr-impl
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Generate the Clang parsed attribute helpers.
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.. option:: -gen-clang-attr-parsed-attr-kinds
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Generate a Clang parsed attribute kinds.
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.. option:: -gen-clang-attr-text-node-dump
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Generate Clang attribute text node dumper.
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.. option:: -gen-clang-attr-node-traverse
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Generate Clang attribute traverser.
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.. option:: -gen-clang-diags-defs
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Generate Clang diagnostics definitions.
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.. option:: -clang-component component
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Only use warnings from specified component.
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.. option:: -gen-clang-diag-groups
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Generate Clang diagnostic groups.
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.. option:: -gen-clang-diags-index-name
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Generate Clang diagnostic name index.
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.. option:: -gen-clang-basic-reader
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Generate Clang BasicReader classes.
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.. option:: -gen-clang-basic-writer
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Generate Clang BasicWriter classes.
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.. option:: -gen-clang-comment-nodes
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Generate Clang AST comment nodes.
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.. option:: -gen-clang-decl-nodes
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Generate Clang AST declaration nodes.
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.. option:: -gen-clang-stmt-nodes
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Generate Clang AST statement nodes.
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.. option:: -gen-clang-type-nodes
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Generate Clang AST type nodes.
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.. option:: -gen-clang-type-reader
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Generate Clang AbstractTypeReader class.
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.. option:: -gen-clang-type-writer
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Generate Clang AbstractTypeWriter class.
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.. option:: -gen-clang-opcodes
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Generate Clang constexpr interpreter opcodes.
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.. option:: -gen-clang-sa-checkers
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Generate Clang static analyzer checkers.
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.. option:: -gen-clang-comment-html-tags
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Generate efficient matchers for HTML tag names that are used in
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documentation comments.
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.. option:: -gen-clang-comment-html-tags-properties
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Generate efficient matchers for HTML tag properties.
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.. option:: -gen-clang-comment-html-named-character-references
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Generate function to translate named character references to UTF-8 sequences.
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.. option:: -gen-clang-comment-command-info
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Generate command properties for commands that are used in documentation comments.
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.. option:: -gen-clang-comment-command-list
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Generate list of commands that are used in documentation comments.
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.. option:: -gen-clang-opencl-builtins
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Generate OpenCL builtin declaration handlers.
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.. option:: -gen-arm-neon
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Generate ``arm_neon.h`` for Clang.
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.. option:: -gen-arm-fp16
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Generate ``arm_fp16.h`` for Clang.
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.. option:: -gen-arm-bf16
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Generate ``arm_bf16.h`` for Clang.
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.. option:: -gen-arm-neon-sema
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Generate ARM NEON sema support for Clang.
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.. option:: -gen-arm-neon-test
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Generate ARM NEON tests for Clang.
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.. option:: -gen-arm-sve-header
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Generate ``arm_sve.h`` for Clang.
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.. option:: -gen-arm-sve-builtins
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Generate ``arm_sve_builtins.inc`` for Clang.
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.. option:: -gen-arm-sve-builtin-codegen
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Generate ``arm_sve_builtin_cg_map.inc`` for Clang.
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.. option:: -gen-arm-sve-typeflags
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Generate ``arm_sve_typeflags.inc`` for Clang.
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.. option:: -gen-arm-sve-sema-rangechecks
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Generate ``arm_sve_sema_rangechecks.inc`` for Clang.
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.. option:: -gen-arm-mve-header
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Generate ``arm_mve.h`` for Clang.
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.. option:: -gen-arm-mve-builtin-def
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Generate ARM MVE builtin definitions for Clang.
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.. option:: -gen-arm-mve-builtin-sema
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Generate ARM MVE builtin sema checks for Clang.
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.. option:: -gen-arm-mve-builtin-codegen
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Generate ARM MVE builtin code-generator for Clang.
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.. option:: -gen-arm-mve-builtin-aliases
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Generate list of valid ARM MVE builtin aliases for Clang.
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.. option:: -gen-arm-cde-header
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|
||||
Generate ``arm_cde.h`` for Clang.
|
||||
|
||||
.. option:: -gen-arm-cde-builtin-def
|
||||
|
||||
Generate ARM CDE builtin definitions for Clang.
|
||||
|
||||
.. option:: -gen-arm-cde-builtin-sema
|
||||
|
||||
Generate ARM CDE builtin sema checks for Clang.
|
||||
|
||||
.. option:: -gen-arm-cde-builtin-codegen
|
||||
|
||||
Generate ARM CDE builtin code-generator for Clang.
|
||||
|
||||
.. option:: -gen-arm-cde-builtin-aliases
|
||||
|
||||
Generate list of valid ARM CDE builtin aliases for Clang.
|
||||
|
||||
.. option:: -gen-attr-docs
|
||||
|
||||
Generate attribute documentation.
|
||||
|
||||
.. option:: -gen-diag-docs
|
||||
|
||||
Generate diagnostic documentation.
|
||||
|
||||
.. option:: -gen-opt-docs
|
||||
|
||||
Generate option documentation.
|
||||
|
||||
.. option:: -gen-clang-data-collectors
|
||||
|
||||
Generate data collectors for AST nodes.
|
||||
|
||||
.. option:: -gen-clang-test-pragma-attribute-supported-attributes
|
||||
|
||||
Generate a list of attributes supported by ``#pragma`` Clang attribute for
|
||||
testing purposes.
|
||||
|
||||
|
||||
|
||||
mlir-tblgen Options
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
.. option:: -gen-avail-interface-decls
|
||||
|
||||
Generate availability interface declarations.
|
||||
|
||||
.. option:: -gen-avail-interface-defs
|
||||
|
||||
Generate op interface definitions.
|
||||
|
||||
.. option:: -gen-dialect-doc
|
||||
|
||||
Generate dialect documentation.
|
||||
|
||||
.. option:: -dialect
|
||||
|
||||
The dialect to generate.
|
||||
|
||||
.. option:: -gen-directive-decl
|
||||
|
||||
Generate declarations for directives (OpenMP, etc.).
|
||||
|
||||
.. option:: -gen-enum-decls
|
||||
|
||||
Generate enum utility declarations.
|
||||
|
||||
.. option:: -gen-enum-defs
|
||||
|
||||
Generate enum utility definitions.
|
||||
|
||||
.. option:: -gen-enum-from-llvmir-conversions
|
||||
|
||||
Generate conversions of EnumAttrs from LLVM IR.
|
||||
|
||||
.. option:: -gen-enum-to-llvmir-conversions
|
||||
|
||||
Generate conversions of EnumAttrs to LLVM IR.
|
||||
|
||||
.. option:: -gen-llvmir-conversions
|
||||
|
||||
Generate LLVM IR conversions.
|
||||
|
||||
.. option:: -gen-llvmir-intrinsics
|
||||
|
||||
Generate LLVM IR intrinsics.
|
||||
|
||||
.. option:: -llvmir-intrinsics-filter
|
||||
|
||||
Only keep the intrinsics with the specified substring in their record name.
|
||||
|
||||
.. option:: -dialect-opclass-base
|
||||
|
||||
The base class for the ops in the dialect we are to emit.
|
||||
|
||||
.. option:: -gen-op-decls
|
||||
|
||||
Generate operation declarations.
|
||||
|
||||
.. option:: -gen-op-defs
|
||||
|
||||
Generate operation definitions.
|
||||
|
||||
.. option:: -asmformat-error-is-fatal
|
||||
|
||||
Emit a fatal error if format parsing fails.
|
||||
|
||||
.. option:: -op-exclude-regex
|
||||
|
||||
Regular expression of name of ops to exclude (no filter if empty).
|
||||
|
||||
.. option:: -op-include-regex
|
||||
|
||||
Regular expression of name of ops to include (no filter if empty).
|
||||
|
||||
.. option:: -gen-op-doc
|
||||
|
||||
Generate operation documentation.
|
||||
|
||||
.. option:: -gen-pass-decls
|
||||
|
||||
Generate operation documentation.
|
||||
|
||||
.. option:: -name namestring
|
||||
|
||||
The name of this group of passes.
|
||||
|
||||
.. option:: -gen-pass-doc
|
||||
|
||||
Generate pass documentation.
|
||||
|
||||
.. option:: -gen-rewriters
|
||||
|
||||
Generate pattern rewriters.
|
||||
|
||||
.. option:: -gen-spirv-avail-impls
|
||||
|
||||
Generate SPIR-V operation utility definitions.
|
||||
|
||||
.. option:: -gen-spirv-capability-implication
|
||||
|
||||
Generate utility function to return implied capabilities for a given capability.
|
||||
|
||||
.. option:: -gen-spirv-enum-avail-decls
|
||||
|
||||
Generate SPIR-V enum availability declarations.
|
||||
|
||||
.. option:: -gen-spirv-enum-avail-defs
|
||||
|
||||
Generate SPIR-V enum availability definitions.
|
||||
|
||||
.. option:: -gen-spirv-op-utils
|
||||
|
||||
Generate SPIR-V operation utility definitions.
|
||||
|
||||
.. option:: -gen-spirv-serialization
|
||||
|
||||
Generate SPIR-V (de)serialization utilities and functions.
|
||||
|
||||
.. option:: -gen-struct-attr-decls
|
||||
|
||||
Generate struct utility declarations.
|
||||
|
||||
.. option:: -gen-struct-attr-defs
|
||||
|
||||
Generate struct utility definitions.
|
||||
|
||||
.. option:: -gen-typedef-decls
|
||||
|
||||
Generate TypeDef declarations.
|
||||
|
||||
.. option:: -gen-typedef-defs
|
||||
|
||||
Generate TypeDef definitions.
|
||||
|
||||
.. option:: -typedefs-dialect name
|
||||
|
||||
Generate types for this dialect.
|
||||
|
||||
EXIT STATUS
|
||||
-----------
|
||||
|
||||
If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error
|
||||
If :program:`xxx-tblgen` succeeds, it will exit with 0. Otherwise, if an error
|
||||
occurs, it will exit with a non-zero value.
|
||||
|
||||
@ -1,31 +0,0 @@
|
||||
=====================
|
||||
TableGen Deficiencies
|
||||
=====================
|
||||
|
||||
.. contents::
|
||||
:local:
|
||||
|
||||
Introduction
|
||||
============
|
||||
|
||||
Despite being very generic, TableGen has some deficiencies that have been
|
||||
pointed out numerous times. The common theme is that, while TableGen allows
|
||||
you to build Domain-Specific-Languages, the final languages that you create
|
||||
lack the power of other DSLs, which in turn increase considerably the size
|
||||
and complexity of TableGen files.
|
||||
|
||||
At the same time, TableGen allows you to create virtually any meaning of
|
||||
the basic concepts via custom-made back-ends, which can pervert the original
|
||||
design and make it very hard for newcomers to understand it.
|
||||
|
||||
There are some in favour of extending the semantics even more, but making sure
|
||||
back-ends adhere to strict rules. Others suggesting we should move to more
|
||||
powerful DSLs designed with specific purposes, or even re-using existing
|
||||
DSLs.
|
||||
|
||||
Known Problems
|
||||
==============
|
||||
|
||||
TODO: Add here frequently asked questions about why TableGen doesn't do
|
||||
what you want, how it might, and how we could extend/restrict it to
|
||||
be more use friendly.
|
||||
@ -21,8 +21,11 @@ and generate one or more output files. These output files are typically
|
||||
developer needs.
|
||||
|
||||
This document describes the LLVM TableGen facility in detail. It is intended
|
||||
for the programmer who is using TableGen to produce tables for a project. If
|
||||
you are looking for a simple overview, check out :doc:`TableGen Overview <./index>`.
|
||||
for the programmer who is using TableGen to produce code for a project. If
|
||||
you are looking for a simple overview, check out the :doc:`TableGen Overview
|
||||
<./index>`. The various ``xxx-tblgen`` commands used to invoke TableGen are
|
||||
described in :doc:`xxx-tblgen: Target Description to C++ Code
|
||||
<../CommandGuide/tblgen>`.
|
||||
|
||||
An example of a backend is ``RegisterInfo``, which generates the register
|
||||
file information for a particular target machine, for use by the LLVM
|
||||
@ -1662,9 +1665,10 @@ and non-0 as true.
|
||||
|
||||
``!subst(``\ *target*\ ``,`` *repl*\ ``,`` *value*\ ``)``
|
||||
This operator replaces all occurrences of the *target* in the *value* with
|
||||
the *repl* and produces the resulting value. For strings, this is straightforward.
|
||||
the *repl* and produces the resulting value. The *value* can
|
||||
be a string, in which case substring substitution is performed.
|
||||
|
||||
If the arguments are record names, the function produces the *repl*
|
||||
The *value* can be a record name, in which case the operator produces the *repl*
|
||||
record if the *target* record name equals the *value* record name; otherwise it
|
||||
produces the *value*.
|
||||
|
||||
|
||||
@ -23,10 +23,12 @@ for common features of these records to be factored out. This reduces the
|
||||
amount of duplication in the description, reduces the chance of error, and makes
|
||||
it easier to structure domain specific information.
|
||||
|
||||
The core part of TableGen parses a file, instantiates the declarations, and
|
||||
hands the result off to a domain-specific `backend`_ for processing.
|
||||
See the :doc:`TableGen Programmer's Reference <./ProgRef>` for an in-depth
|
||||
description of TableGen.
|
||||
The TableGen front end parses a file, instantiates the declarations, and
|
||||
hands the result off to a domain-specific `backend`_ for processing. See
|
||||
the :doc:`TableGen Programmer's Reference <./ProgRef>` for an in-depth
|
||||
description of TableGen. See :doc:`xxx-tblgen: Target Description to C++
|
||||
Code <../CommandGuide/tblgen>` for details on the various
|
||||
``xxx-tblgen`` commands that invoke TableGen.
|
||||
|
||||
The current major users of TableGen are :doc:`The LLVM Target-Independent
|
||||
Code Generator <../CodeGenerator>` and the `Clang diagnostics and attributes
|
||||
@ -286,7 +288,7 @@ TableGen Deficiencies
|
||||
|
||||
Despite being very generic, TableGen has some deficiencies that have been
|
||||
pointed out numerous times. The common theme is that, while TableGen allows
|
||||
you to build Domain-Specific-Languages, the final languages that you create
|
||||
you to build domain specific languages, the final languages that you create
|
||||
lack the power of other DSLs, which in turn increase considerably the size
|
||||
and complexity of TableGen files.
|
||||
|
||||
@ -295,10 +297,7 @@ the basic concepts via custom-made backends, which can pervert the original
|
||||
design and make it very hard for newcomers to understand the evil TableGen
|
||||
file.
|
||||
|
||||
There are some in favour of extending the semantics even more, but making sure
|
||||
There are some in favor of extending the semantics even more, but making sure
|
||||
backends adhere to strict rules. Others are suggesting we should move to less,
|
||||
more powerful DSLs designed with specific purposes, or even re-using existing
|
||||
more powerful DSLs designed with specific purposes, or even reusing existing
|
||||
DSLs.
|
||||
|
||||
Either way, this is a discussion that will likely span across several years,
|
||||
if not decades. You can read more in :doc:`TableGen Deficiencies <./Deficiencies>`.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user