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[Hexagon] Remove vectors of i64 from valid HVX types

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HVX does not support operations on 64-bit integers.

llvm-svn: 320722
This commit is contained in:
Krzysztof Parzyszek 2017-12-14 18:35:24 +00:00
parent 421445fcbf
commit f4e269a95c
5 changed files with 24 additions and 69 deletions
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59
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -129,18 +129,10 @@ namespace {
// Implement calling convention for Hexagon. // Implement calling convention for Hexagon.
static const MVT LegalV64[] = { static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
}; static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
static const MVT LegalW64[] = { static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64
};
static const MVT LegalV128[] = {
MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64
};
static const MVT LegalW128[] = {
MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64
};
static bool static bool
CC_Hexagon(unsigned ValNo, MVT ValVT, CC_Hexagon(unsigned ValNo, MVT ValVT,
@ -235,19 +227,19 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false; return false;
} }
if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || if (LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
LocVT == MVT::v64i8 || LocVT == MVT::v512i1) { LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
Offset = State.AllocateStack(64, 64); Offset = State.AllocateStack(64, 64);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false; return false;
} }
if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || if (LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) { LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
Offset = State.AllocateStack(128, 128); Offset = State.AllocateStack(128, 128);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false; return false;
} }
if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || if (LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
LocVT == MVT::v256i8) { LocVT == MVT::v256i8) {
Offset = State.AllocateStack(256, 256); Offset = State.AllocateStack(256, 256);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
@ -370,7 +362,7 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
auto &HST = MF.getSubtarget<HexagonSubtarget>(); auto &HST = MF.getSubtarget<HexagonSubtarget>();
if (HST.useHVX64BOps() && if (HST.useHVX64BOps() &&
(LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || (LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) { LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
if (unsigned Reg = State.AllocateReg(VecLstS)) { if (unsigned Reg = State.AllocateReg(VecLstS)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
@ -380,7 +372,7 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
return false; return false;
} }
if (HST.useHVX64BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || if (HST.useHVX64BOps() && (LocVT == MVT::v32i32 ||
LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) { LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) {
if (unsigned Reg = State.AllocateReg(VecLstD)) { if (unsigned Reg = State.AllocateReg(VecLstD)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
@ -391,7 +383,7 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
return false; return false;
} }
// 128B Mode // 128B Mode
if (HST.useHVX128BOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || if (HST.useHVX128BOps() && (LocVT == MVT::v64i32 ||
LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) { LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) {
if (unsigned Reg = State.AllocateReg(VecLstD)) { if (unsigned Reg = State.AllocateReg(VecLstD)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
@ -402,7 +394,7 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
return false; return false;
} }
if (HST.useHVX128BOps() && if (HST.useHVX128BOps() &&
(LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || (LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) { LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
if (unsigned Reg = State.AllocateReg(VecLstS)) { if (unsigned Reg = State.AllocateReg(VecLstS)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
@ -442,19 +434,18 @@ static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
LocVT = MVT::i64; LocVT = MVT::i64;
LocInfo = CCValAssign::BCvt; LocInfo = CCValAssign::BCvt;
} else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 || } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
LocVT == MVT::v16i32 || LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v512i1) {
LocVT == MVT::v512i1) {
LocVT = MVT::v16i32; LocVT = MVT::v16i32;
ValVT = MVT::v16i32; ValVT = MVT::v16i32;
LocInfo = CCValAssign::Full; LocInfo = CCValAssign::Full;
} else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 || } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || LocVT == MVT::v32i32 ||
(LocVT == MVT::v1024i1 && HST.useHVX128BOps())) { (LocVT == MVT::v1024i1 && HST.useHVX128BOps())) {
LocVT = MVT::v32i32; LocVT = MVT::v32i32;
ValVT = MVT::v32i32; ValVT = MVT::v32i32;
LocInfo = CCValAssign::Full; LocInfo = CCValAssign::Full;
} else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 || } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
LocVT == MVT::v64i32 || LocVT == MVT::v32i64) { LocVT == MVT::v64i32) {
LocVT = MVT::v64i32; LocVT = MVT::v64i32;
ValVT = MVT::v64i32; ValVT = MVT::v64i32;
LocInfo = CCValAssign::Full; LocInfo = CCValAssign::Full;
@ -932,10 +923,10 @@ static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget()); auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
bool ValidHVX128BType = bool ValidHVX128BType =
HST.useHVX128BOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 || HST.useHVX128BOps() && (VT == MVT::v32i32 ||
VT == MVT::v64i16 || VT == MVT::v128i8); VT == MVT::v64i16 || VT == MVT::v128i8);
bool ValidHVXType = bool ValidHVXType =
HST.useHVX64BOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 || HST.useHVX64BOps() && (VT == MVT::v16i32 ||
VT == MVT::v32i16 || VT == MVT::v64i8); VT == MVT::v32i16 || VT == MVT::v64i8);
if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT == MVT::i32 || if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT == MVT::i32 ||
@ -1167,14 +1158,14 @@ SDValue HexagonTargetLowering::LowerFormalArguments(
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
// Single Vector // Single Vector
} else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || } else if ((RegVT == MVT::v16i32 ||
RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
unsigned VReg = unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg); RegInfo.addLiveIn(VA.getLocReg(), VReg);
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
} else if (Subtarget.useHVX128BOps() && } else if (Subtarget.useHVX128BOps() &&
((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || ((RegVT == MVT::v32i32 ||
RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
unsigned VReg = unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
@ -1182,14 +1173,14 @@ SDValue HexagonTargetLowering::LowerFormalArguments(
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
// Double Vector // Double Vector
} else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || } else if ((RegVT == MVT::v32i32 ||
RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
unsigned VReg = unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass); RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg); RegInfo.addLiveIn(VA.getLocReg(), VReg);
InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
} else if (Subtarget.useHVX128BOps() && } else if (Subtarget.useHVX128BOps() &&
((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || ((RegVT == MVT::v64i32 ||
RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
unsigned VReg = unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass); RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
@ -1738,21 +1729,17 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v8i64, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass); addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass);
} else if (Subtarget.useHVX128BOps()) { } else if (Subtarget.useHVX128BOps()) {
addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v16i64, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v32i64, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass); addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass);
} }
} }
@ -3094,9 +3081,6 @@ bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
case MVT::v16i32: case MVT::v16i32:
case MVT::v32i32: case MVT::v32i32:
case MVT::v64i32: case MVT::v64i32:
case MVT::v8i64:
case MVT::v16i64:
case MVT::v32i64:
return true; return true;
} }
return false; return false;
@ -3114,13 +3098,11 @@ HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
case MVT::v64i8: case MVT::v64i8:
case MVT::v32i16: case MVT::v32i16:
case MVT::v16i32: case MVT::v16i32:
case MVT::v8i64:
RRC = &Hexagon::HvxVRRegClass; RRC = &Hexagon::HvxVRRegClass;
break; break;
case MVT::v128i8: case MVT::v128i8:
case MVT::v64i16: case MVT::v64i16:
case MVT::v32i32: case MVT::v32i32:
case MVT::v16i64:
if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() && if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
Subtarget.useHVX128BOps()) Subtarget.useHVX128BOps())
RRC = &Hexagon::HvxVRRegClass; RRC = &Hexagon::HvxVRRegClass;
@ -3130,7 +3112,6 @@ HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
case MVT::v256i8: case MVT::v256i8:
case MVT::v128i16: case MVT::v128i16:
case MVT::v64i32: case MVT::v64i32:
case MVT::v32i64:
RRC = &Hexagon::HvxWRRegClass; RRC = &Hexagon::HvxWRRegClass;
break; break;
} }

4
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
View File

@ -214,7 +214,7 @@ HexagonTargetLowering::LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG)
SDValue VecV = Op.getOperand(0); SDValue VecV = Op.getOperand(0);
MVT ElemTy = ty(VecV).getVectorElementType(); MVT ElemTy = ty(VecV).getVectorElementType();
unsigned ElemWidth = ElemTy.getSizeInBits(); unsigned ElemWidth = ElemTy.getSizeInBits();
assert(ElemWidth >= 8 && ElemWidth <= 32); // TODO i64 assert(ElemWidth >= 8 && ElemWidth <= 32);
(void)ElemWidth; (void)ElemWidth;
const SDLoc &dl(Op); const SDLoc &dl(Op);
@ -246,7 +246,7 @@ HexagonTargetLowering::LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG)
SDValue IdxV = Op.getOperand(2); SDValue IdxV = Op.getOperand(2);
MVT ElemTy = ty(VecV).getVectorElementType(); MVT ElemTy = ty(VecV).getVectorElementType();
unsigned ElemWidth = ElemTy.getSizeInBits(); unsigned ElemWidth = ElemTy.getSizeInBits();
assert(ElemWidth >= 8 && ElemWidth <= 32); // TODO i64 assert(ElemWidth >= 8 && ElemWidth <= 32);
(void)ElemWidth; (void)ElemWidth;
auto InsertWord = [&DAG,&dl,this] (SDValue VecV, SDValue ValV, auto InsertWord = [&DAG,&dl,this] (SDValue VecV, SDValue ValV,

12
lib/Target/Hexagon/HexagonIntrinsicsV60.td
View File

@ -35,9 +35,6 @@ def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))), def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))),
(v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; (v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
def : Pat <(v512i1 (bitconvert (v8i64 HvxVR:$src1))),
(v512i1 (V6_vandvrt(v8i64 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))), def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
(v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
@ -47,9 +44,6 @@ def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))),
def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))), def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))),
(v64i8 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; (v64i8 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
def : Pat <(v8i64 (bitconvert (v512i1 HvxQR:$src1))),
(v8i64 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))), def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
(v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
@ -59,9 +53,6 @@ def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))), def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))),
(v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
def : Pat <(v1024i1 (bitconvert (v16i64 HvxVR:$src1))),
(v1024i1 (V6_vandvrt (v16i64 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))), def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))),
(v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
@ -71,9 +62,6 @@ def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))), def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))),
(v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
def : Pat <(v16i64 (bitconvert (v1024i1 HvxQR:$src1))),
(v16i64 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
let AddedComplexity = 140 in { let AddedComplexity = 140 in {
def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)), def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)),
(V6_vS32b_ai IntRegs:$addr, 0, (V6_vS32b_ai IntRegs:$addr, 0,

8
lib/Target/Hexagon/HexagonPatterns.td
View File

@ -91,12 +91,10 @@ def V2I32: PatLeaf<(v2i32 DoubleRegs:$R)>;
def HVI8: PatLeaf<(VecI8 HvxVR:$R)>; def HVI8: PatLeaf<(VecI8 HvxVR:$R)>;
def HVI16: PatLeaf<(VecI16 HvxVR:$R)>; def HVI16: PatLeaf<(VecI16 HvxVR:$R)>;
def HVI32: PatLeaf<(VecI32 HvxVR:$R)>; def HVI32: PatLeaf<(VecI32 HvxVR:$R)>;
def HVI64: PatLeaf<(VecI64 HvxVR:$R)>;
def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>; def HWI8: PatLeaf<(VecPI8 HvxWR:$R)>;
def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>; def HWI16: PatLeaf<(VecPI16 HvxWR:$R)>;
def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>; def HWI32: PatLeaf<(VecPI32 HvxWR:$R)>;
def HWI64: PatLeaf<(VecPI64 HvxWR:$R)>;
// Pattern fragments to extract the low and high subregisters from a // Pattern fragments to extract the low and high subregisters from a
// 64-bit value. // 64-bit value.
@ -820,11 +818,9 @@ let Predicates = [HasV60T,UseHVX] in {
def: HvxSel_pat<PS_vselect, HVI8>; def: HvxSel_pat<PS_vselect, HVI8>;
def: HvxSel_pat<PS_vselect, HVI16>; def: HvxSel_pat<PS_vselect, HVI16>;
def: HvxSel_pat<PS_vselect, HVI32>; def: HvxSel_pat<PS_vselect, HVI32>;
def: HvxSel_pat<PS_vselect, HVI64>;
def: HvxSel_pat<PS_wselect, HWI8>; def: HvxSel_pat<PS_wselect, HWI8>;
def: HvxSel_pat<PS_wselect, HWI16>; def: HvxSel_pat<PS_wselect, HWI16>;
def: HvxSel_pat<PS_wselect, HWI32>; def: HvxSel_pat<PS_wselect, HWI32>;
def: HvxSel_pat<PS_wselect, HWI64>;
} }
// From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw). // From LegalizeDAG.cpp: (Pu ? Pv : Pw) <=> (Pu & Pv) | (!Pu & Pw).
@ -2011,7 +2007,6 @@ let Predicates = [UseHVX] in {
defm: HvxLd_pat<MI, Load, VecI8, IsVecOff>; defm: HvxLd_pat<MI, Load, VecI8, IsVecOff>;
defm: HvxLd_pat<MI, Load, VecI16, IsVecOff>; defm: HvxLd_pat<MI, Load, VecI16, IsVecOff>;
defm: HvxLd_pat<MI, Load, VecI32, IsVecOff>; defm: HvxLd_pat<MI, Load, VecI32, IsVecOff>;
defm: HvxLd_pat<MI, Load, VecI64, IsVecOff>;
} }
defm: HvxLdVs_pat<V6_vL32b_nt_ai, alignednontemporalload>; defm: HvxLdVs_pat<V6_vL32b_nt_ai, alignednontemporalload>;
defm: HvxLdVs_pat<V6_vL32b_ai, alignedload>; defm: HvxLdVs_pat<V6_vL32b_ai, alignedload>;
@ -2021,7 +2016,6 @@ let Predicates = [UseHVX] in {
defm: HvxLd_pat<MI, Load, VecPI8, IsVecOff>; defm: HvxLd_pat<MI, Load, VecPI8, IsVecOff>;
defm: HvxLd_pat<MI, Load, VecPI16, IsVecOff>; defm: HvxLd_pat<MI, Load, VecPI16, IsVecOff>;
defm: HvxLd_pat<MI, Load, VecPI32, IsVecOff>; defm: HvxLd_pat<MI, Load, VecPI32, IsVecOff>;
defm: HvxLd_pat<MI, Load, VecPI64, IsVecOff>;
} }
defm: HvxLdWs_pat<PS_vloadrw_nt_ai, alignednontemporalload>; defm: HvxLdWs_pat<PS_vloadrw_nt_ai, alignednontemporalload>;
defm: HvxLdWs_pat<PS_vloadrw_ai, alignedload>; defm: HvxLdWs_pat<PS_vloadrw_ai, alignedload>;
@ -2480,7 +2474,6 @@ let Predicates = [UseHVX] in {
defm: HvxSt_pat<MI, Store, IsVecOff, HVI8>; defm: HvxSt_pat<MI, Store, IsVecOff, HVI8>;
defm: HvxSt_pat<MI, Store, IsVecOff, HVI16>; defm: HvxSt_pat<MI, Store, IsVecOff, HVI16>;
defm: HvxSt_pat<MI, Store, IsVecOff, HVI32>; defm: HvxSt_pat<MI, Store, IsVecOff, HVI32>;
defm: HvxSt_pat<MI, Store, IsVecOff, HVI64>;
} }
defm: HvxStVs_pat<V6_vS32b_nt_ai, alignednontemporalstore>; defm: HvxStVs_pat<V6_vS32b_nt_ai, alignednontemporalstore>;
defm: HvxStVs_pat<V6_vS32b_ai, alignedstore>; defm: HvxStVs_pat<V6_vS32b_ai, alignedstore>;
@ -2490,7 +2483,6 @@ let Predicates = [UseHVX] in {
defm: HvxSt_pat<MI, Store, IsVecOff, HWI8>; defm: HvxSt_pat<MI, Store, IsVecOff, HWI8>;
defm: HvxSt_pat<MI, Store, IsVecOff, HWI16>; defm: HvxSt_pat<MI, Store, IsVecOff, HWI16>;
defm: HvxSt_pat<MI, Store, IsVecOff, HWI32>; defm: HvxSt_pat<MI, Store, IsVecOff, HWI32>;
defm: HvxSt_pat<MI, Store, IsVecOff, HWI64>;
} }
defm: HvxStWs_pat<PS_vstorerw_nt_ai, alignednontemporalstore>; defm: HvxStWs_pat<PS_vstorerw_nt_ai, alignednontemporalstore>;
defm: HvxStWs_pat<PS_vstorerw_ai, alignedstore>; defm: HvxStWs_pat<PS_vstorerw_ai, alignedstore>;

10
lib/Target/Hexagon/HexagonRegisterInfo.td
View File

@ -216,9 +216,6 @@ def VecI16
def VecI32 def VecI32
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v16i32, v16i32, v32i32, v32i32, v16i32]>; [v16i32, v16i32, v32i32, v32i32, v16i32]>;
def VecI64
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v8i64, v8i64, v16i64, v16i64, v8i64]>;
def VecPI8 def VecPI8
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v128i8, v128i8, v256i8, v256i8, v128i8]>; [v128i8, v128i8, v256i8, v256i8, v128i8]>;
@ -228,9 +225,6 @@ def VecPI16
def VecPI32 def VecPI32
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v32i32, v32i32, v64i32, v64i32, v32i32]>; [v32i32, v32i32, v64i32, v64i32, v32i32]>;
def VecPI64
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v16i64, v16i64, v32i64, v32i64, v16i64]>;
// HVX register classes // HVX register classes
@ -257,13 +251,13 @@ def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64,
def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64,
(add D11, D10, D9, D8, D3, D2, D1, D0)>; (add D11, D10, D9, D8, D3, D2, D1, D0)>;
def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32, VecI64], 512, def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32], 512,
(add (sequence "V%u", 0, 31), VTMP)> { (add (sequence "V%u", 0, 31), VTMP)> {
let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
[RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>;
} }
def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32, VecPI64], 1024, def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32], 1024,
(add (sequence "W%u", 0, 15))> { (add (sequence "W%u", 0, 15))> {
let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode],
[RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>; [RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>;