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[mips] MIPS64R6 compact branch support
MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that map to the same instruction, extend compact branch support for the corresponding 64bit branches. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D20164 llvm-svn: 276739
This commit is contained in:
Simon Dardis
parent
5565482780
commit
f4e81c479c
@ -3720,7 +3720,14 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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case Mips::BLTZC:
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case Mips::BEQZC:
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case Mips::BNEZC:
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if (Inst.getOperand(0).getReg() == Mips::ZERO)
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case Mips::BLEZC64:
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case Mips::BGEZC64:
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case Mips::BGTZC64:
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case Mips::BLTZC64:
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case Mips::BEQZC64:
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case Mips::BNEZC64:
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if (Inst.getOperand(0).getReg() == Mips::ZERO ||
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Inst.getOperand(0).getReg() == Mips::ZERO_64)
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return Match_RequiresNoZeroRegister;
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return Match_Success;
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case Mips::BGEC:
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@ -3729,9 +3736,17 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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case Mips::BLTUC:
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case Mips::BEQC:
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case Mips::BNEC:
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if (Inst.getOperand(0).getReg() == Mips::ZERO)
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case Mips::BGEC64:
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case Mips::BLTC64:
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case Mips::BGEUC64:
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case Mips::BLTUC64:
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case Mips::BEQC64:
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case Mips::BNEC64:
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if (Inst.getOperand(0).getReg() == Mips::ZERO ||
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Inst.getOperand(0).getReg() == Mips::ZERO_64)
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return Match_RequiresNoZeroRegister;
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if (Inst.getOperand(1).getReg() == Mips::ZERO)
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if (Inst.getOperand(1).getReg() == Mips::ZERO ||
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Inst.getOperand(1).getReg() == Mips::ZERO_64)
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return Match_RequiresNoZeroRegister;
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if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
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return Match_RequiresDifferentOperands;
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@ -129,7 +129,8 @@ void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
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unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
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unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
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if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC) {
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if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||
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Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {
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assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
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if (Reg0 < Reg1)
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return;
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@ -141,7 +142,7 @@ void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
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if (Reg1 >= Reg0)
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return;
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} else
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llvm_unreachable("Cannot rewrite unknown branch!");
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llvm_unreachable("Cannot rewrite unknown branch!");
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Inst.getOperand(0).setReg(RegOp1);
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Inst.getOperand(1).setReg(RegOp0);
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@ -210,6 +211,8 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
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// Compact branches, enforce encoding restrictions.
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case Mips::BEQC:
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case Mips::BNEC:
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case Mips::BEQC64:
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case Mips::BNEC64:
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case Mips::BOVC:
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case Mips::BOVC_MMR6:
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case Mips::BNVC:
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@ -76,6 +76,19 @@ class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
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class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
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class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
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class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
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class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
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class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
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class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
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class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
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class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
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class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
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class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
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class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
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class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
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class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>;
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class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>;
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class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
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GPR64Opnd> {
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bit isCall = 1;
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@ -130,10 +143,28 @@ let AdditionalPredicates = [NotInMicroMips],
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def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;
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def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;
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}
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let isCodeGenOnly = 1 in {
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def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
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def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
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let DecoderNamespace = "Mips32r6_64r6_GP64" in {
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// Jump and Branch Instructions
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def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64;
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def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64;
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def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64;
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def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64;
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def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64;
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def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64;
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def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64;
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def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64;
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def BLTC64 : BLTC_ENC, BLTC64_DESC, ISA_MIPS64R6, GPR_64;
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def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64;
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def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64;
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def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64;
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}
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let DecoderNamespace = "Mips32r6_64r6_BranchZero" in {
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def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64;
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def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Aliases
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@ -341,6 +341,22 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
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return Mips::BLTUC;
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case Mips::BLTZ:
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return Mips::BLTZC;
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case Mips::BEQ64:
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if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
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return 0;
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return Mips::BEQC64;
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case Mips::BNE64:
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if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
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return 0;
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return Mips::BNEC64;
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case Mips::BGTZ64:
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return Mips::BGTZC64;
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case Mips::BGEZ64:
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return Mips::BGEZC64;
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case Mips::BLTZ64:
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return Mips::BLTZC64;
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case Mips::BLEZ64:
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return Mips::BLEZC64;
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// For MIPSR6, the instruction 'jic' can be used for these cases. Some
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// tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
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case Mips::JR:
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@ -403,7 +419,7 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
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MachineBasicBlock::iterator I) const {
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MachineInstrBuilder MIB;
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// Certain branches have two forms: e.g beq $1, $zero, dst vs beqz $1, dest
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// Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
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// Pick the zero form of the branch for readable assembly and for greater
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// branch distance in non-microMIPS mode.
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// FIXME: Certain atomic sequences on mips64 generate 32bit references to
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@ -429,6 +445,12 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
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case Mips::BLTC:
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NewOpc = Mips::BLTZC;
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break;
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case Mips::BEQC64:
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NewOpc = Mips::BEQZC64;
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break;
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case Mips::BNEC64:
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NewOpc = Mips::BNEZC64;
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break;
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}
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}
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@ -433,6 +433,18 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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case Mips::BGEZC: return Mips::BLTZC;
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case Mips::BLTZC: return Mips::BGEZC;
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case Mips::BLEZC: return Mips::BGTZC;
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case Mips::BEQZC64: return Mips::BNEZC64;
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case Mips::BNEZC64: return Mips::BEQZC64;
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case Mips::BEQC64: return Mips::BNEC64;
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case Mips::BNEC64: return Mips::BEQC64;
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case Mips::BGEC64: return Mips::BLTC64;
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case Mips::BGEUC64: return Mips::BLTUC64;
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case Mips::BLTC64: return Mips::BGEC64;
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case Mips::BLTUC64: return Mips::BGEUC64;
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case Mips::BGTZC64: return Mips::BLEZC64;
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case Mips::BGEZC64: return Mips::BLTZC64;
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case Mips::BLTZC64: return Mips::BGEZC64;
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case Mips::BLEZC64: return Mips::BGTZC64;
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}
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}
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@ -518,8 +530,12 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
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Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC ||
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Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC ||
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Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC ||
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Opc == Mips::BEQZC || Opc == Mips::BNEZC ||
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Opc == Mips::BC) ? Opc : 0;
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Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BEQZC64 ||
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Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
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Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
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Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
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Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
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Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
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}
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void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
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@ -1,4 +1,6 @@
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; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
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; RUN: llc -march=mips64 -mcpu=mips64r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
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; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
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; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc.
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@ -12,6 +14,7 @@
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; may simplify out the crucical bnec $4, $4 instruction.
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define internal void @_ZL14TestRemoveLastv(i32* %alist.sroa.0.4) {
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; CHECK-LABEL: _ZL14TestRemoveLastv:
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entry:
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%ascevgep = getelementptr i32, i32* %alist.sroa.0.4, i64 99
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br label %do.body121
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@ -45,6 +48,43 @@ do.end146:
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%alnot151 = icmp eq i32 %a9, %a10
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br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
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}
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define internal void @_ZL14TestRemoveLastv64(i64* %alist.sroa.0.4) {
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; CHECK-LABEL: _ZL14TestRemoveLastv64:
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entry:
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%ascevgep = getelementptr i64, i64* %alist.sroa.0.4, i64 99
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br label %do.body121
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for.cond117:
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%alsr.iv.next = add nsw i64 %alsr.iv, -1
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%ascevgep340 = getelementptr i64, i64* %alsr.iv339, i64 -1
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%acmp118 = icmp sgt i64 %alsr.iv.next, 0
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br i1 %acmp118, label %do.body121, label %if.then143
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do.body121:
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%alsr.iv339 = phi i64* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ]
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%alsr.iv = phi i64 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ]
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%a9 = add i64 %alsr.iv, -1
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%alnot124 = icmp eq i64 %alsr.iv, %alsr.iv
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br i1 %alnot124, label %do.body134, label %if.then143, !prof !11
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do.body134:
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%a10 = add i64 %alsr.iv, -1
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%a11 = load i64, i64* %alsr.iv339, align 4, !tbaa !5
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; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]]
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; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
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%alnot137 = icmp eq i64 %a9, %a11
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br i1 %alnot137, label %do.end146, label %if.then143, !prof !11
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if.then143:
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ret void
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unreachable
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do.end146:
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%alnot151 = icmp eq i64 %a9, %a10
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br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
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}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C++ TBAA"}
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194
test/CodeGen/Mips/compactbranches/compact-branches-64.ll
Normal file
194
test/CodeGen/Mips/compactbranches/compact-branches-64.ll
Normal file
@ -0,0 +1,194 @@
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; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
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; Function Attrs: nounwind
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define void @l() {
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entry:
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; CHECK-LABEL: l:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
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; CHECK: jalrc $25
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%call1 = tail call i64 @j()
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%cmp = icmp eq i64 %call, %call1
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; CHECK: bnec
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: jalrc $25
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tail call void @f(i64 signext -2)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jrc $ra
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ret void
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}
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declare i64 @k()
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declare i64 @j()
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declare void @f(i64 signext)
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; Function Attrs: define void @l2() {
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define void @l2() {
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entry:
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; CHECK-LABEL: l2:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
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; CHECK: jalrc $25
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%call1 = tail call i64 @i()
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%cmp = icmp eq i64 %call, %call1
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; CHECK: beqc
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br i1 %cmp, label %if.end, label %if.then
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if.then: ; preds = %entry:
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; CHECK: jalrc $25
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tail call void @f(i64 signext -1)
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br label %if.end
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if.end: ; preds = %entry, %if.then
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; CHECK: jrc $ra
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ret void
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}
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declare i64 @i()
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; Function Attrs: nounwind
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define void @l3() {
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entry:
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; CHECK-LABEL: l3:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
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%cmp = icmp slt i64 %call, 0
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; CHECK: bgez
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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; CHECK: jalrc $25
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tail call void @f(i64 signext 0)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jrc $ra
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ret void
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}
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; Function Attrs: nounwind
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define void @l4() {
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entry:
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; CHECK-LABEL: l4:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
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%cmp = icmp slt i64 %call, 1
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; CHECK: bgtzc
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry:
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tail call void @f(i64 signext 1)
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br label %if.end
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if.end: ; preds = %if.then, %entry
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; CHECK: jrc $ra
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ret void
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}
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; Function Attrs: nounwind
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define void @l5() {
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entry:
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; CHECK-LABEL: l5:
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; CHECK: jalrc $25
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%call = tail call i64 @k()
|
||||
%cmp = icmp sgt i64 %call, 0
|
||||
; CHECK: blezc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; CHECK: jalrc $25
|
||||
tail call void @f(i64 signext 2)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l6() {
|
||||
entry:
|
||||
; CHECK-LABEL: l6:
|
||||
; CHECK: jalrc $25
|
||||
%call = tail call i64 @k()
|
||||
%cmp = icmp sgt i64 %call, -1
|
||||
; CHECK: bltzc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; CHECK: jalrc $25
|
||||
tail call void @f(i64 signext 3)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l7() {
|
||||
entry:
|
||||
; CHECK-LABEL: l7:
|
||||
; CHECK: jalrc $25
|
||||
%call = tail call i64 @k()
|
||||
%cmp = icmp eq i64 %call, 0
|
||||
; CHECK: bnezc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; CHECK: jalrc $25
|
||||
tail call void @f(i64 signext 4)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @l8() {
|
||||
entry:
|
||||
; CHECK-LABEL: l8:
|
||||
; CHECK: jalrc $25
|
||||
%call = tail call i64 @k()
|
||||
%cmp = icmp eq i64 %call, 0
|
||||
; CHECK: beqzc
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
|
||||
if.then: ; preds = %entry:
|
||||
; CHECK: jalrc $25
|
||||
tail call void @f(i64 signext 5)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
; CHECK: jrc $ra
|
||||
ret void
|
||||
}
|
||||
|
||||
define i64 @l9(i8* ()* %i) {
|
||||
entry:
|
||||
; CHECK-LABEL: l9:
|
||||
%i.addr = alloca i8* ()*, align 4
|
||||
store i8* ()* %i, i8* ()** %i.addr, align 4
|
||||
; CHECK: jalrc $25
|
||||
%call = call i64 @k()
|
||||
%cmp = icmp ne i64 %call, 0
|
||||
; CHECK: beqzc
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%0 = load i8* ()*, i8* ()** %i.addr, align 4
|
||||
; CHECK: jalrc $25
|
||||
%call1 = call i8* %0()
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
; CHECK: jrc $ra
|
||||
ret i64 -1
|
||||
}
|
||||
@ -1,11 +1,14 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s \
|
||||
; RUN: -filetype=obj -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
|
||||
; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s -filetype=obj \
|
||||
; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
|
||||
; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
|
||||
; RUN: llc -march=mips -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s -filetype=obj \
|
||||
; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
|
||||
|
||||
; bnezc and beqzc have restriction that $rt != 0
|
||||
|
||||
define i32 @f() {
|
||||
; CHECK-LABEL: f
|
||||
; CHECK-LABEL: f:
|
||||
; CHECK-NOT: bnezc $0
|
||||
|
||||
%cmp = icmp eq i32 1, 1
|
||||
@ -19,7 +22,7 @@ define i32 @f() {
|
||||
}
|
||||
|
||||
define i32 @f1() {
|
||||
; CHECK-LABEL: f1
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK-NOT: beqzc $0
|
||||
|
||||
%cmp = icmp eq i32 0, 0
|
||||
@ -37,7 +40,7 @@ define i32 @f1() {
|
||||
; beqc and bnec have the restriction that $rs < $rt.
|
||||
|
||||
define i32 @f2(i32 %a, i32 %b) {
|
||||
; ENCODING-LABEL: f2
|
||||
; ENCODING-LABEL: f2:
|
||||
; ENCODING-NOT: beqc $5, $4
|
||||
; ENCODING-NOT: bnec $5, $4
|
||||
|
||||
@ -51,3 +54,49 @@ define i32 @f2(i32 %a, i32 %b) {
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
define i64 @f3() {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK-NOT: bnezc $0
|
||||
|
||||
%cmp = icmp eq i64 1, 1
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i64 1
|
||||
|
||||
if.end:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
define i64 @f4() {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK-NOT: beqzc $0
|
||||
|
||||
%cmp = icmp eq i64 0, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i64 1
|
||||
|
||||
if.end:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
; We silently fixup cases where the register allocator or user has given us
|
||||
; an instruction with incorrect operands that is trivially acceptable.
|
||||
; beqc and bnec have the restriction that $rs < $rt.
|
||||
|
||||
define i64 @f5(i64 %a, i64 %b) {
|
||||
; ENCODING-LABEL: f5:
|
||||
; ENCODING-NOT: beqc $5, $4
|
||||
; ENCODING-NOT: bnec $5, $4
|
||||
|
||||
%cmp = icmp eq i64 %b, %a
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then:
|
||||
ret i64 1
|
||||
|
||||
if.end:
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user