RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Code Issues Projects Releases Wiki Activity

AMDGPU: Fix missing writelane cases to skip with exec=0

Browse Source
This commit is contained in:
Matt Arsenault 2020-10-16 20:33:02 -04:00
parent ea587e3fff
commit f52c63425c
2 changed files with 55 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -3108,7 +3108,8 @@ bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
//
// However, executing them with EXEC = 0 causes them to operate on undefined
// data, which we avoid by returning true here.
if (Opcode == AMDGPU::V_READFIRSTLANE_B32 || Opcode == AMDGPU::V_READLANE_B32)
if (Opcode == AMDGPU::V_READFIRSTLANE_B32 ||
Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32)
return true;
return false;

53
test/CodeGen/AMDGPU/remove-short-exec-branches-mode-def.mir → test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
View File

@ -109,3 +109,56 @@ body: |
bb.2:
S_ENDPGM 0
...
---
name: need_skip_writelane_b32
body: |
; CHECK-LABEL: name: need_skip_writelane_b32
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: $sgpr0 = IMPLICIT_DEF
; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0
; CHECK: bb.2:
; CHECK: S_ENDPGM 0
bb.0:
successors: %bb.1, %bb.2
S_CBRANCH_EXECZ %bb.2, implicit $exec
bb.1:
successors: %bb.2
$sgpr0 = IMPLICIT_DEF
$vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0
bb.2:
S_ENDPGM 0
...
---
name: need_skip_readlane_b32
body: |
; CHECK-LABEL: name: need_skip_readlane_b32
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: $vgpr0 = IMPLICIT_DEF
; CHECK: $sgpr0 = V_READLANE_B32 $vgpr0, 0
; CHECK: bb.2:
; CHECK: S_ENDPGM 0
bb.0:
successors: %bb.1, %bb.2
S_CBRANCH_EXECZ %bb.2, implicit $exec
bb.1:
successors: %bb.2
$vgpr0 = IMPLICIT_DEF
$sgpr0 = V_READLANE_B32 $vgpr0, 0
bb.2:
S_ENDPGM 0
...