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[GlobalISel][AArch64] Add IRTranslator support for G_FCOS and G_FSIN

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This adds IRTranslator support for the G_FCOS and G_FSIN generic instructions.

https://reviews.llvm.org/D57197
2/3

llvm-svn: 352401
This commit is contained in:
Jessica Paquette 2019-01-28 18:34:17 +00:00
parent e2b76b0235
commit f54ac2d77f
2 changed files with 26 additions and 0 deletions
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10
lib/CodeGen/GlobalISel/IRTranslator.cpp
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@ -1055,6 +1055,16 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::cos:
MIRBuilder.buildInstr(TargetOpcode::G_FCOS)
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
case Intrinsic::sin:
MIRBuilder.buildInstr(TargetOpcode::G_FSIN)
.addDef(getOrCreateVReg(CI))
.addUse(getOrCreateVReg(*CI.getArgOperand(0)));
return true;
}
return false;
}

16
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
View File

@ -2293,3 +2293,19 @@ define <2 x double> @test_ceil_v2f64(<2 x double> %x) {
%y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x)
ret <2 x double> %y
}
declare float @llvm.cos.f32(float)
define float @test_cos_f32(float %x) {
; CHECK-LABEL: name: test_cos_f32
; CHECK: %{{[0-9]+}}:_(s32) = G_FCOS %{{[0-9]+}}
%y = call float @llvm.cos.f32(float %x)
ret float %y
}
declare float @llvm.sin.f32(float)
define float @test_sin_f32(float %x) {
; CHECK-LABEL: name: test_sin_f32
; CHECK: %{{[0-9]+}}:_(s32) = G_FSIN %{{[0-9]+}}
%y = call float @llvm.sin.f32(float %x)
ret float %y
}