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Revert r157755.

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The commit is intended to fix rdar://11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.

llvm-svn: 158122
This commit is contained in:
Manman Ren 2012-06-06 23:53:03 +00:00
parent e89b370473
commit f591de61da
5 changed files with 0 additions and 61 deletions
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8
include/llvm/Target/TargetInstrInfo.h
View File

@ -640,14 +640,6 @@ public:
return false;
}
/// OptimizeSubInstr - See if the SUB instruction can be converted into
/// something more efficient E.g., on X86, we can replace SUB with CMP
/// if the actual result of SUB is not used.
virtual bool OptimizeSubInstr(MachineInstr *SubInstr,
const MachineRegisterInfo *MRI) const {
return false;
}
/// FoldImmediate - 'Reg' is known to be defined by a move immediate
/// instruction, try to fold the immediate into the use instruction.
virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,

1
lib/CodeGen/PeepholeOptimizer.cpp
View File

@ -472,7 +472,6 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (SeenMoveImm)
Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
}
Changed |= TII->OptimizeSubInstr(MI, MRI);
First = false;
PMII = MII;

38
lib/Target/X86/X86InstrInfo.cpp
View File

@ -2793,44 +2793,6 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
NewMIs.push_back(MIB);
}
bool X86InstrInfo::
OptimizeSubInstr(MachineInstr *SubInstr, const MachineRegisterInfo *MRI) const {
// If destination is a memory operand, do not perform this optimization.
if ((SubInstr->getOpcode() != X86::SUB64rr) &&
(SubInstr->getOpcode() != X86::SUB32rr) &&
(SubInstr->getOpcode() != X86::SUB16rr) &&
(SubInstr->getOpcode() != X86::SUB8rr) &&
(SubInstr->getOpcode() != X86::SUB64ri32) &&
(SubInstr->getOpcode() != X86::SUB64ri8) &&
(SubInstr->getOpcode() != X86::SUB32ri) &&
(SubInstr->getOpcode() != X86::SUB32ri8) &&
(SubInstr->getOpcode() != X86::SUB16ri) &&
(SubInstr->getOpcode() != X86::SUB16ri8) &&
(SubInstr->getOpcode() != X86::SUB8ri))
return false;
unsigned DestReg = SubInstr->getOperand(0).getReg();
if (MRI->use_begin(DestReg) != MRI->use_end())
return false;
// There is no use of the destination register, we can replace SUB with CMP.
switch (SubInstr->getOpcode()) {
default: break;
case X86::SUB64rr: SubInstr->setDesc(get(X86::CMP64rr)); break;
case X86::SUB32rr: SubInstr->setDesc(get(X86::CMP32rr)); break;
case X86::SUB16rr: SubInstr->setDesc(get(X86::CMP16rr)); break;
case X86::SUB8rr: SubInstr->setDesc(get(X86::CMP8rr)); break;
case X86::SUB64ri32: SubInstr->setDesc(get(X86::CMP64ri32)); break;
case X86::SUB64ri8: SubInstr->setDesc(get(X86::CMP64ri8)); break;
case X86::SUB32ri: SubInstr->setDesc(get(X86::CMP32ri)); break;
case X86::SUB32ri8: SubInstr->setDesc(get(X86::CMP32ri8)); break;
case X86::SUB16ri: SubInstr->setDesc(get(X86::CMP16ri)); break;
case X86::SUB16ri8: SubInstr->setDesc(get(X86::CMP16ri8)); break;
case X86::SUB8ri: SubInstr->setDesc(get(X86::CMP8ri)); break;
}
SubInstr->RemoveOperand(0);
return true;
}
/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
/// instruction with two undef reads of the register being defined. This is
/// used for mapping:

3
lib/Target/X86/X86InstrInfo.h
View File

@ -364,9 +364,6 @@ public:
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI, unsigned UseIdx) const;
virtual bool OptimizeSubInstr(MachineInstr *SubInstr,
const MachineRegisterInfo *MRI) const;
private:
MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
MachineFunction::iterator &MFI,

11
test/CodeGen/X86/jump_sign.ll
View File

@ -83,14 +83,3 @@ entry:
%cond = select i1 %cmp, i32 %sub, i32 0
ret i32 %cond
}
; rdar://11540023
define i64 @n(i64 %x, i64 %y) nounwind {
entry:
; CHECK: n:
; CHECK-NOT: sub
; CHECK: cmp
%sub = sub nsw i64 %x, %y
%cmp = icmp slt i64 %sub, 0
%y.x = select i1 %cmp, i64 %y, i64 %x
ret i64 %y.x
}