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ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684 llvm-svn: 144301
This commit is contained in:
Jim Grosbach
parent
e9f2479115
commit
f5943e4c5e
@ -544,6 +544,14 @@ def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
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let ParserMatchClass = Imm0_31AsmOperand;
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}
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/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
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def Imm0_32AsmOperand: AsmOperandClass { let Name = "Imm0_32"; }
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def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
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return Imm >= 0 && Imm < 32;
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}]> {
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let ParserMatchClass = Imm0_32AsmOperand;
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}
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/// imm0_255 predicate - Immediate in the range [0,255].
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def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
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def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
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@ -5001,5 +5009,14 @@ def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
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// encoding. It seems we should be able to do that sort of thing
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// in tblgen, but it could get ugly.
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def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
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(ins GPR:$Rd, GPR:$Rm, imm1_32:$imm, pred:$p,
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(ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
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cc_out:$s)>;
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def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
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(ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
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cc_out:$s)>;
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def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
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(ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
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cc_out:$s)>;
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def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
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(ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
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cc_out:$s)>;
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@ -602,6 +602,14 @@ public:
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int64_t Value = CE->getValue();
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return Value > 0 && Value < 33;
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}
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bool isImm0_32() const {
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if (Kind != k_Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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return Value >= 0 && Value < 33;
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}
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bool isImm0_65535() const {
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if (Kind != k_Immediate)
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return false;
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@ -1217,6 +1225,11 @@ public:
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Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
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}
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void addImm0_32Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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}
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void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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@ -4542,14 +4555,28 @@ processInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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switch (Inst.getOpcode()) {
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// Handle the MOV complex aliases.
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case ARM::ASRi: {
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unsigned Amt = Inst.getOperand(2).getImm() + 1;
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unsigned ShiftOp = ARM_AM::getSORegOpc(ARM_AM::asr, Amt);
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case ARM::ASRi:
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case ARM::LSRi:
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case ARM::LSLi:
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case ARM::RORi: {
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ARM_AM::ShiftOpc ShiftTy;
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unsigned Amt = Inst.getOperand(2).getImm();
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switch(Inst.getOpcode()) {
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default: llvm_unreachable("unexpected opcode!");
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case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
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case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
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case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
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case ARM::RORi: ShiftTy = ARM_AM::ror; break;
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}
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// A shift by zero is a plain MOVr, not a MOVsi.
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unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
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unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::MOVsi);
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TmpInst.setOpcode(Opc);
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TmpInst.addOperand(Inst.getOperand(0)); // Rd
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(MCOperand::CreateImm(ShiftOp)); // Shift value and ty
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if (Opc == ARM::MOVsi)
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TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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TmpInst.addOperand(Inst.getOperand(5)); // cc_out
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@ -261,9 +261,11 @@ Lforward:
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@------------------------------------------------------------------------------
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asr r2, r4, #32
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asr r2, r4, #2
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asr r2, r4, #0
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@ CHECK: asr r2, r4, #32 @ encoding: [0x44,0x20,0xa0,0xe1]
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@ CHECK: asr r2, r4, #2 @ encoding: [0x44,0x21,0xa0,0xe1]
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@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
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@------------------------------------------------------------------------------
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@ -787,11 +789,28 @@ Lforward:
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@ CHECK: ldrhthi r8, [r11], #0 @ encoding: [0xb0,0x80,0xfb,0x80]
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@------------------------------------------------------------------------------
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@ FIXME: LSL
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@ LSL
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@------------------------------------------------------------------------------
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lsl r2, r4, #31
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lsl r2, r4, #1
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lsl r2, r4, #0
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@ CHECK: lsl r2, r4, #31 @ encoding: [0x84,0x2f,0xa0,0xe1]
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@ CHECK: lsl r2, r4, #1 @ encoding: [0x84,0x20,0xa0,0xe1]
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@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
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@------------------------------------------------------------------------------
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@ FIXME: LSR
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@ LSR
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@------------------------------------------------------------------------------
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lsr r2, r4, #32
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lsr r2, r4, #2
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lsr r2, r4, #0
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@ CHECK: lsr r2, r4, #32 @ encoding: [0x24,0x20,0xa0,0xe1]
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@ CHECK: lsr r2, r4, #2 @ encoding: [0x24,0x21,0xa0,0xe1]
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@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
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@------------------------------------------------------------------------------
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@ MCR/MCR2
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@ -1319,6 +1338,18 @@ Lforward:
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@ CHECK: rfeia r1! @ encoding: [0x00,0x0a,0xb1,0xf8]
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@------------------------------------------------------------------------------
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@ ROR
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@------------------------------------------------------------------------------
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ror r2, r4, #31
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ror r2, r4, #1
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ror r2, r4, #0
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@ CHECK: ror r2, r4, #31 @ encoding: [0xe4,0x2f,0xa0,0xe1]
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@ CHECK: ror r2, r4, #1 @ encoding: [0xe4,0x20,0xa0,0xe1]
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@ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1]
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@------------------------------------------------------------------------------
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@ RSB
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@------------------------------------------------------------------------------
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@ -24,13 +24,9 @@
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@ Out of range immediates for ASR instruction.
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asrs r2, r3, #33
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asrs r2, r3, #0
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: asrs r2, r3, #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: asrs r2, r3, #0
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@ CHECK-ERRORS: ^
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@ Out of range immediates for BKPT instruction.
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bkpt #256
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