diff --git a/test/CodeGen/ARM/crash-greedy.ll b/test/CodeGen/ARM/crash-greedy.ll index 444505f8786..bd0f85556b8 100644 --- a/test/CodeGen/ARM/crash-greedy.ll +++ b/test/CodeGen/ARM/crash-greedy.ll @@ -7,11 +7,11 @@ target triple = "thumbv7-apple-darwin" declare double @exp(double) ; CHECK: remat_subreg -define void @remat_subreg(float* nocapture %x, i32* %y, i32 %n, i32 %z, float %c, float %lambda, float* nocapture %ret_f, float* nocapture %ret_df) nounwind { +define void @remat_subreg(float* nocapture %x, i32* %y, i32 %n, i32 %z, float %c, float %lambda, float* nocapture %ret_f, float* nocapture %ret_df, i1 %cond) nounwind { entry: %conv16 = fpext float %lambda to double %mul17 = fmul double %conv16, -1.000000e+00 - br i1 undef, label %cond.end.us, label %cond.end + br i1 %cond, label %cond.end.us, label %cond.end cond.end.us: ; preds = %entry unreachable diff --git a/test/CodeGen/Hexagon/bit-visit-flowq.ll b/test/CodeGen/Hexagon/bit-visit-flowq.ll index b44847dee68..f0786da3bed 100644 --- a/test/CodeGen/Hexagon/bit-visit-flowq.ll +++ b/test/CodeGen/Hexagon/bit-visit-flowq.ll @@ -9,7 +9,7 @@ target triple = "hexagon" @debug = external hidden unnamed_addr global i1, align 4 ; Function Attrs: nounwind -define void @foo() local_unnamed_addr #0 { +define void @foo(i1 %cond) local_unnamed_addr #0 { entry: br label %if.end5 @@ -17,14 +17,14 @@ if.end5: ; preds = %entry br i1 undef, label %if.then12, label %if.end13 if.then12: ; preds = %if.end5 - unreachable + ret void if.end13: ; preds = %if.end5 br label %for.cond for.cond: ; preds = %if.end13 %or.cond288 = or i1 undef, undef - br i1 undef, label %if.then44, label %if.end51 + br i1 %cond, label %if.then44, label %if.end51 if.then44: ; preds = %for.cond tail call void @bar() #0 diff --git a/test/CodeGen/Hexagon/rdf-ignore-undef.ll b/test/CodeGen/Hexagon/rdf-ignore-undef.ll index 5d72318f420..d52676b0e87 100644 --- a/test/CodeGen/Hexagon/rdf-ignore-undef.ll +++ b/test/CodeGen/Hexagon/rdf-ignore-undef.ll @@ -49,7 +49,7 @@ if.end88.do.body_crit_edge: ; preds = %if.end88 br label %do.body if.then124: ; preds = %if.end88, %do.body - unreachable + ret i32 0 } attributes #0 = { nounwind } diff --git a/test/CodeGen/Hexagon/reg-scavengebug.ll b/test/CodeGen/Hexagon/reg-scavengebug.ll index 16e7cfe2a07..d53799bc4d1 100644 --- a/test/CodeGen/Hexagon/reg-scavengebug.ll +++ b/test/CodeGen/Hexagon/reg-scavengebug.ll @@ -19,7 +19,7 @@ declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #0 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #0 ; Function Attrs: nounwind -define void @f0(i16* noalias nocapture %a0, i32* noalias nocapture readonly %a1, i32 %a2, i8* noalias nocapture readonly %a3) #1 { +define void @f0(i16* noalias nocapture %a0, i32* noalias nocapture readonly %a1, i32 %a2, i8* noalias nocapture readonly %a3, i1 %cond) #1 { b0: %v0 = add nsw i32 %a2, 63 %v1 = ashr i32 %v0, 6 @@ -40,7 +40,7 @@ b1: ; preds = %b0 %v13 = getelementptr inbounds i32, i32* %a1, i32 48 %v14 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v12, <16 x i32> undef) %v15 = bitcast i32* %v13 to <16 x i32>* - br i1 undef, label %b2, label %b3 + br i1 %cond, label %b2, label %b3 b2: ; preds = %b1 %v16 = getelementptr inbounds <16 x i32>, <16 x i32>* %v15, i32 1 diff --git a/test/CodeGen/Hexagon/regalloc-block-overlap.ll b/test/CodeGen/Hexagon/regalloc-block-overlap.ll index c4f490196bb..90b37f2a0d7 100644 --- a/test/CodeGen/Hexagon/regalloc-block-overlap.ll +++ b/test/CodeGen/Hexagon/regalloc-block-overlap.ll @@ -16,7 +16,7 @@ declare <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32>, <32 x i32>, i32) declare <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32>, <32 x i32>, i32) #1 declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #1 -define hidden void @fred(<32 x i32>* %a0, i32 %a1) #0 { +define hidden void @fred(<32 x i32>* %a0, i32 %a1, i1 %cond) #0 { b0: %v1 = ashr i32 %a1, 7 %v2 = shl nsw i32 %v1, 7 @@ -70,7 +70,7 @@ b15: ; preds = %b14 br label %b16 b16: ; preds = %b15 - br i1 undef, label %b17, label %b18 + br i1 %cond, label %b17, label %b18 b17: ; preds = %b16 unreachable diff --git a/test/Transforms/LoopVectorize/if-pred-stores.ll b/test/Transforms/LoopVectorize/if-pred-stores.ll index 8dd12f5d30c..353087f66e5 100644 --- a/test/Transforms/LoopVectorize/if-pred-stores.ll +++ b/test/Transforms/LoopVectorize/if-pred-stores.ll @@ -194,9 +194,11 @@ for.end: ; vectorized loop body. ; PR18724 -define void @bug18724() { +define void @bug18724(i1 %cond) { ; UNROLL-LABEL: @bug18724( ; UNROLL-NEXT: entry: +; UNROLL-NEXT: [[TMP0:%.*]] = xor i1 [[COND:%.*]], true +; UNROLL-NEXT: call void @llvm.assume(i1 [[TMP0]]) ; UNROLL-NEXT: br label [[FOR_BODY14:%.*]] ; UNROLL: for.body14: ; UNROLL-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], [[FOR_INC23:%.*]] ], [ undef, [[ENTRY:%.*]] ] @@ -211,13 +213,16 @@ define void @bug18724() { ; UNROLL: for.inc23: ; UNROLL-NEXT: [[INEWCHUNKS_2]] = phi i32 [ [[INC21]], [[IF_THEN18]] ], [ [[INEWCHUNKS_120]], [[FOR_BODY14]] ] ; UNROLL-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], 1 +; UNROLL-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV3]] to i32 +; UNROLL-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP1]], 0 +; UNROLL-NEXT: call void @llvm.assume(i1 [[CMP13]]) ; UNROLL-NEXT: br label [[FOR_BODY14]] ; ; UNROLL-NOSIMPLIFY-LABEL: @bug18724( ; UNROLL-NOSIMPLIFY-NEXT: entry: ; UNROLL-NOSIMPLIFY-NEXT: br label [[FOR_BODY9:%.*]] ; UNROLL-NOSIMPLIFY: for.body9: -; UNROLL-NOSIMPLIFY-NEXT: br i1 undef, label [[FOR_INC26:%.*]], label [[FOR_BODY14_PREHEADER:%.*]] +; UNROLL-NOSIMPLIFY-NEXT: br i1 [[COND:%.*]], label [[FOR_INC26:%.*]], label [[FOR_BODY14_PREHEADER:%.*]] ; UNROLL-NOSIMPLIFY: for.body14.preheader: ; UNROLL-NOSIMPLIFY-NEXT: br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; UNROLL-NOSIMPLIFY: vector.ph: @@ -287,6 +292,8 @@ define void @bug18724() { ; ; VEC-LABEL: @bug18724( ; VEC-NEXT: entry: +; VEC-NEXT: [[TMP0:%.*]] = xor i1 [[COND:%.*]], true +; VEC-NEXT: call void @llvm.assume(i1 [[TMP0]]) ; VEC-NEXT: br label [[FOR_BODY14:%.*]] ; VEC: for.body14: ; VEC-NEXT: [[INDVARS_IV3:%.*]] = phi i64 [ [[INDVARS_IV_NEXT4:%.*]], [[FOR_INC23:%.*]] ], [ undef, [[ENTRY:%.*]] ] @@ -301,13 +308,16 @@ define void @bug18724() { ; VEC: for.inc23: ; VEC-NEXT: [[INEWCHUNKS_2]] = phi i32 [ [[INC21]], [[IF_THEN18]] ], [ [[INEWCHUNKS_120]], [[FOR_BODY14]] ] ; VEC-NEXT: [[INDVARS_IV_NEXT4]] = add nsw i64 [[INDVARS_IV3]], 1 +; VEC-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV3]] to i32 +; VEC-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP1]], 0 +; VEC-NEXT: call void @llvm.assume(i1 [[CMP13]]) ; VEC-NEXT: br label [[FOR_BODY14]] ; entry: br label %for.body9 for.body9: - br i1 undef, label %for.inc26, label %for.body14 + br i1 %cond, label %for.inc26, label %for.body14 for.body14: %indvars.iv3 = phi i64 [ %indvars.iv.next4, %for.inc23 ], [ undef, %for.body9 ]