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[llvm-exegesis] Add support for AVX512 explicit rounding operands.

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Reviewers: gchatelet

Subscribers: tschuett, mstojanovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73083
This commit is contained in:
Clement Courbet 2020-01-21 10:12:13 +01:00
parent f9cfdda9d4
commit f5fc494b30
2 changed files with 22 additions and 0 deletions
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4
tools/llvm-exegesis/lib/X86/Target.cpp
View File

@ -636,6 +636,10 @@ void ExegesisX86Target::randomizeMCOperand(
const Operand &Op = Instr.getPrimaryOperand(Var);
switch (Op.getExplicitOperandInfo().OperandType) {
case X86::OperandType::OPERAND_ROUNDING_CONTROL:
AssignedValue =
MCOperand::createImm(randomIndex(X86::STATIC_ROUNDING::NO_EXC));
break;
case X86::OperandType::OPERAND_COND_CODE:
AssignedValue =
MCOperand::createImm(randomIndex(X86::CondCode::LAST_VALID_COND));

18
unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
View File

@ -198,6 +198,24 @@ TEST_F(SerialSnippetGeneratorTest, LAHF) {
}
}
TEST_F(SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
// - VCVTUSI642SDZrrb_Int
// - Op0 Explicit Def RegClass(VR128X)
// - Op1 Explicit Use RegClass(VR128X)
// - Op2 Explicit Use STATIC_ROUNDING
// - Op2 Explicit Use RegClass(GR64)
// - Op4 Implicit Use Reg(MXSCR)
const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int;
const Instruction &Instr = State.getIC().getInstr(Opcode);
auto Configs =
Generator.generateConfigurations(Instr, State.getRATC().emptyRegisters());
ASSERT_FALSE(Configs.takeError());
ASSERT_THAT(*Configs, SizeIs(1));
const BenchmarkCode &BC = (*Configs)[0];
ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
}
TEST_F(ParallelSnippetGeneratorTest, ParallelInstruction) {
// - BNDCL32rr
// - Op0 Explicit Use RegClass(BNDR)