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[GlobalISel] Add G_SBFX/G_UBFX to computeKnownBits
Differential Revision: https://reviews.llvm.org/D102969
This commit is contained in:
Brendon Cahoon
parent
6b76b629b6
commit
f5ff020d9c
@ -113,6 +113,20 @@ void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1,
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Known = KnownBits::commonBits(Known, Known2);
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}
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// Bitfield extract is computed as (Src >> Offset) & Mask, where Mask is
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// created using Width. Use this function when the inputs are KnownBits
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// objects. TODO: Move this KnownBits.h if this is usable in more cases.
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static KnownBits extractBits(unsigned BitWidth, const KnownBits &SrcOpKnown,
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const KnownBits &OffsetKnown,
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const KnownBits &WidthKnown) {
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KnownBits Mask(BitWidth);
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Mask.Zero = APInt::getBitsSetFrom(
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BitWidth, WidthKnown.getMaxValue().getLimitedValue(BitWidth));
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Mask.One = APInt::getLowBitsSet(
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BitWidth, WidthKnown.getMinValue().getLimitedValue(BitWidth));
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return KnownBits::lshr(SrcOpKnown, OffsetKnown) & Mask;
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}
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void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
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const APInt &DemandedElts,
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unsigned Depth) {
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@ -495,6 +509,34 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
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Known.reverseBits();
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break;
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}
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case TargetOpcode::G_UBFX: {
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KnownBits SrcOpKnown, OffsetKnown, WidthKnown;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), OffsetKnown, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(3).getReg(), WidthKnown, DemandedElts,
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Depth + 1);
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Known = extractBits(BitWidth, SrcOpKnown, OffsetKnown, WidthKnown);
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break;
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}
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case TargetOpcode::G_SBFX: {
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KnownBits SrcOpKnown, OffsetKnown, WidthKnown;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), OffsetKnown, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(3).getReg(), WidthKnown, DemandedElts,
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Depth + 1);
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Known = extractBits(BitWidth, SrcOpKnown, OffsetKnown, WidthKnown);
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// Sign extend the extracted value using shift left and arithmetic shift
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// right.
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KnownBits ExtKnown = KnownBits::makeConstant(APInt(BitWidth, BitWidth));
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KnownBits ShiftKnown = KnownBits::computeForAddSub(
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/*Add*/ false, /*NSW*/ false, ExtKnown, WidthKnown);
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Known = KnownBits::ashr(KnownBits::shl(Known, ShiftKnown), ShiftKnown);
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break;
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}
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}
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assert(!Known.hasConflict() && "Bits known to be one AND zero?");
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@ -1670,3 +1670,191 @@ TEST_F(AArch64GISelMITest, TestKnownBitsAssertZext) {
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EXPECT_EQ(0u, Res.One.getZExtValue());
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EXPECT_EQ(0xFFFFFFFFFFFFFFF8u, Res.Zero.getZExtValue());
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}
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TEST_F(AMDGPUGISelMITest, TestKnownBitsUBFX) {
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StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
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" %4:_(s32) = G_CONSTANT i32 12\n"
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" %5:_(s32) = G_CONSTANT i32 8\n"
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" %6:_(s32) = G_UBFX %3, %4(s32), %5\n"
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" %ubfx_copy:_(s32) = COPY %6\n"
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" %7:_(s32) = G_CONSTANT i32 28672\n"
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" %8:_(s32) = G_UBFX %7, %4(s32), %5\n"
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" %ubfx_copy_val:_(s32) = COPY %8\n"
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" %9:_(s32) = G_IMPLICIT_DEF\n"
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" %10:_(s32) = G_IMPLICIT_DEF\n"
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" %11:_(s32) = G_UBFX %3, %9(s32), %10\n"
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" %ubfx_copy_unk:_(s32) = COPY %11\n"
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" %12:_(s32) = G_UBFX %3, %9(s32), %5\n"
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" %ubfx_copy_unk_off:_(s32) = COPY %12\n"
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" %13:_(s32) = G_UBFX %3, %4(s32), %10\n"
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" %ubfx_copy_unk_width:_(s32) = COPY %13\n";
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setUp(MIRString);
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if (!TM)
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return;
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Register CopyBfxReg = Copies[Copies.size() - 5];
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Register CopyValBfxReg = Copies[Copies.size() - 4];
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Register CopyUnkBfxReg = Copies[Copies.size() - 3];
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Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
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Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
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MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);
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Register SrcReg = CopyBfx->getOperand(1).getReg();
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MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);
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Register ValSrcReg = CopyValBfx->getOperand(1).getReg();
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MachineInstr *CopyUnkBfx = MRI->getVRegDef(CopyUnkBfxReg);
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Register UnkSrcReg = CopyUnkBfx->getOperand(1).getReg();
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MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);
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Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();
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MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);
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Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();
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GISelKnownBits Info(*MF);
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KnownBits Res1 = Info.getKnownBits(SrcReg);
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EXPECT_EQ(0u, Res1.One.getZExtValue());
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EXPECT_EQ(0xffffff00u, Res1.Zero.getZExtValue());
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KnownBits Res2 = Info.getKnownBits(ValSrcReg);
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EXPECT_EQ(7u, Res2.One.getZExtValue());
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EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());
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KnownBits Res3 = Info.getKnownBits(UnkSrcReg);
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EXPECT_EQ(0u, Res3.One.getZExtValue());
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EXPECT_EQ(0u, Res3.Zero.getZExtValue());
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KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);
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EXPECT_EQ(0u, Res4.One.getZExtValue());
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EXPECT_EQ(0xffffff00u, Res4.Zero.getZExtValue());
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KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);
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EXPECT_EQ(0u, Res5.One.getZExtValue());
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EXPECT_EQ(0xfff00000u, Res5.Zero.getZExtValue());
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}
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TEST_F(AMDGPUGISelMITest, TestKnownBitsSBFX) {
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StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
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" %4:_(s32) = G_CONSTANT i32 8\n"
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" %5:_(s32) = G_CONSTANT i32 4\n"
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" %6:_(s32) = G_SBFX %3, %4(s32), %5\n"
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" %sbfx_copy:_(s32) = COPY %6\n"
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" %7:_(s32) = G_CONSTANT i32 2047\n"
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" %8:_(s32) = G_SBFX %7, %4(s32), %5\n"
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" %sbfx_copy_val:_(s32) = COPY %8\n"
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" %9:_(s32) = G_CONSTANT i32 2048\n"
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" %10:_(s32) = G_SBFX %9, %4(s32), %5\n"
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" %sbfx_copy_neg_val:_(s32) = COPY %10\n"
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" %11:_(s32) = G_IMPLICIT_DEF\n"
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" %12:_(s32) = G_SBFX %7, %11(s32), %5\n"
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" %sbfx_copy_unk_off:_(s32) = COPY %12\n"
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" %13:_(s32) = G_SBFX %9, %4(s32), %11\n"
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" %sbfx_copy_unk_width:_(s32) = COPY %13\n";
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setUp(MIRString);
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if (!TM)
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return;
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Register CopyBfxReg = Copies[Copies.size() - 5];
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Register CopyValBfxReg = Copies[Copies.size() - 4];
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Register CopyNegValBfxReg = Copies[Copies.size() - 3];
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Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
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Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
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MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);
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Register SrcReg = CopyBfx->getOperand(1).getReg();
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MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);
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Register ValSrcReg = CopyValBfx->getOperand(1).getReg();
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MachineInstr *CopyNegValBfx = MRI->getVRegDef(CopyNegValBfxReg);
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Register NegValSrcReg = CopyNegValBfx->getOperand(1).getReg();
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MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);
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Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();
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MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);
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Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();
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GISelKnownBits Info(*MF);
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KnownBits Res1 = Info.getKnownBits(SrcReg);
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EXPECT_EQ(0u, Res1.One.getZExtValue());
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EXPECT_EQ(0u, Res1.Zero.getZExtValue());
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KnownBits Res2 = Info.getKnownBits(ValSrcReg);
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EXPECT_EQ(7u, Res2.One.getZExtValue());
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EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());
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KnownBits Res3 = Info.getKnownBits(NegValSrcReg);
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EXPECT_EQ(0xfffffff8u, Res3.One.getZExtValue());
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EXPECT_EQ(7u, Res3.Zero.getZExtValue());
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KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);
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EXPECT_EQ(0u, Res4.One.getZExtValue());
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EXPECT_EQ(0u, Res4.Zero.getZExtValue());
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KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);
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EXPECT_EQ(0u, Res5.One.getZExtValue());
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EXPECT_EQ(0u, Res5.Zero.getZExtValue());
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}
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TEST_F(AMDGPUGISelMITest, TestNumSignBitsUBFX) {
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StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
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" %4:_(s32) = G_CONSTANT i32 12\n"
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" %5:_(s32) = G_CONSTANT i32 8\n"
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" %6:_(s32) = G_UBFX %3, %4(s32), %5\n"
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" %ubfx_copy_unk:_(s32) = COPY %6\n"
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" %7:_(s32) = G_CONSTANT i32 28672\n"
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" %8:_(s32) = G_UBFX %7, %4(s32), %5\n"
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" %ubfx_copy_pos:_(s32) = COPY %8\n"
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" %9:_(s32) = G_CONSTANT i32 -1\n"
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" %10:_(s32) = G_UBFX %9, %4(s32), %5\n"
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" %ubfx_copy_neg:_(s32) = COPY %10\n"
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" %11:_(s32) = G_IMPLICIT_DEF\n"
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" %12:_(s32) = G_UBFX %7, %11(s32), %5\n"
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" %ubfx_copy_unk_off:_(s32) = COPY %12\n"
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" %13:_(s32) = G_UBFX %7, %4(s32), %11\n"
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" %ubfx_copy_unk_width:_(s32) = COPY %13\n";
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setUp(MIRString);
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if (!TM)
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return;
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Register CopyUnkBfxReg = Copies[Copies.size() - 5];
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Register CopyPosBfxReg = Copies[Copies.size() - 4];
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Register CopyNegBfxReg = Copies[Copies.size() - 3];
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Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
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Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
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GISelKnownBits Info(*MF);
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EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkBfxReg));
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EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));
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EXPECT_EQ(24u, Info.computeNumSignBits(CopyNegBfxReg));
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EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkOffBfxReg));
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EXPECT_EQ(29u, Info.computeNumSignBits(CopyUnkWidthBfxReg));
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}
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TEST_F(AMDGPUGISelMITest, TestNumSignBitsSBFX) {
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StringRef MIRString = " %3:_(s32) = G_CONSTANT i32 -1\n"
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" %4:_(s32) = G_CONSTANT i32 8\n"
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" %5:_(s32) = G_CONSTANT i32 4\n"
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" %6:_(s32) = G_SBFX %3, %4(s32), %5\n"
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" %sbfx_copy_neg:_(s32) = COPY %6\n"
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" %7:_(s32) = G_CONSTANT i32 2047\n"
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" %8:_(s32) = G_SBFX %7, %4(s32), %5\n"
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" %sbfx_copy_pos:_(s32) = COPY %8\n"
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" %9:_(s32) = G_CONSTANT i32 2048\n"
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" %10:_(s32) = G_SBFX %9, %4(s32), %5\n"
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" %sbfx_copy_hiset:_(s32) = COPY %10\n"
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" %11:_(s32) = G_IMPLICIT_DEF\n"
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" %12:_(s32) = G_SBFX %11, %4(s32), %5\n"
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" %sbfx_copy_unk:_(s32) = COPY %12\n"
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" %13:_(s32) = G_SBFX %3, %11(s32), %5\n"
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" %sbfx_copy_unk_off:_(s32) = COPY %13\n";
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setUp(MIRString);
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if (!TM)
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return;
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Register CopyNegBfxReg = Copies[Copies.size() - 5];
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Register CopyPosBfxReg = Copies[Copies.size() - 4];
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Register CopyHiSetBfxReg = Copies[Copies.size() - 3];
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Register CopyUnkValBfxReg = Copies[Copies.size() - 2];
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Register CopyUnkOffBfxReg = Copies[Copies.size() - 1];
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GISelKnownBits Info(*MF);
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EXPECT_EQ(32u, Info.computeNumSignBits(CopyNegBfxReg));
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EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));
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EXPECT_EQ(29u, Info.computeNumSignBits(CopyHiSetBfxReg));
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EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkValBfxReg));
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EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkOffBfxReg));
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}
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