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Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.

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llvm-svn: 146709
This commit is contained in:
Eli Friedman 2011-12-15 23:46:18 +00:00
parent f961e224ec
commit f626b19bda
3 changed files with 10 additions and 3 deletions
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2
lib/Target/X86/X86InstrFormats.td
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@ -510,7 +510,7 @@ class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
// FMA4 Instruction Templates
class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern>
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
// XOP 2, 3 and 4 Operand Instruction Template

4
lib/Target/X86/X86InstrSSE.td
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@ -6563,14 +6563,14 @@ let Constraints = "$src1 = $dst" in {
multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
RegisterClass RC, X86MemOperand x86memop,
PatFrag mem_frag, Intrinsic IntId> {
def rr : I<opc, MRMSrcReg, (outs RC:$dst),
def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
def rm : I<opc, MRMSrcMem, (outs RC:$dst),
def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, x86memop:$src2, RC:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),

7
test/MC/X86/x86_64-avx-encoding.s
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@ -3346,3 +3346,10 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
_foo:
nop
vpshufb _foo(%rip), %xmm0, %xmm0
// CHECK: vblendvps %ymm1, _foo2(%rip), %ymm0, %ymm0
// CHECK: encoding: [0xc4,0xe3,0x7d,0x4a,0x05,A,A,A,A,0x10]
// CHECK: fixup A - offset: 5, value: _foo2-5
_foo2:
nop
vblendvps %ymm1, _foo2(%rip), %ymm0, %ymm0