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Add bunch of reg-imm movs
llvm-svn: 75921
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349c4f3410
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@ -56,6 +56,12 @@ namespace {
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return CurDAG->getTargetConstant(Imm, MVT::i16);
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDValue getI32Imm(uint64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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// Include the pieces autogenerated from the target description.
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#include "SystemZGenDAGISel.inc"
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@ -45,6 +45,16 @@ def HH16 : SDNodeXForm<imm, [{
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return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
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}]>;
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def LO32 : SDNodeXForm<imm, [{
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// Transformation function: return low 32 bits.
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return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
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}]>;
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def HI32 : SDNodeXForm<imm, [{
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// Transformation function: return bits 32-63.
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return getI32Imm(N->getZExtValue() >> 32);
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}]>;
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def i64ll16 : PatLeaf<(i64 imm), [{
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// i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
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// bits set.
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@ -73,6 +83,24 @@ def immSExt16 : PatLeaf<(i64 imm), [{
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return ((int64_t)val == (int16_t)val);
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}]>;
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def immSExt32 : PatLeaf<(i64 imm), [{
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// immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
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// field.
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uint64_t val = N->getZExtValue();
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return ((int64_t)val == (int32_t)val);
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}]>;
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def i64lo32 : PatLeaf<(i64 imm), [{
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// i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
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// bits set.
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return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
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}], LO32>;
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def i64hi32 : PatLeaf<(i64 imm), [{
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// i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
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return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
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}], HI32>;
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions...
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//
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@ -97,6 +125,29 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"lghi\t{$dst, $src}",
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[(set GR64:$dst, immSExt16:$src)]>;
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def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"llill\t{$dst, $src}",
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[(set GR64:$dst, i64ll16:$src)]>;
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def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"llilh\t{$dst, $src}",
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[(set GR64:$dst, i64lh16:$src)]>;
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def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"llihl\t{$dst, $src}",
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[(set GR64:$dst, i64hl16:$src)]>;
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def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"llihh\t{$dst, $src}",
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[(set GR64:$dst, i64hh16:$src)]>;
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// FIXME: these 3 instructions seem to require extimm facility
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def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"lgfi\t{$dst, $src}",
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[(set GR64:$dst, immSExt32:$src)]>;
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def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"llilf\t{$dst, $src}",
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[(set GR64:$dst, i64lo32:$src)]>;
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def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"llihf\t{$dst, $src}",
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[(set GR64:$dst, i64hi32:$src)]>;
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}
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//===----------------------------------------------------------------------===//
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@ -1,6 +1,49 @@
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; RUN: llvm-as < %s | llc -march=systemz
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; RUN: llvm-as < %s | llc -march=systemz | grep lghi | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep llill | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep llilh | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep llihl | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep llihh | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep lgfi | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
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; RUN: llvm-as < %s | llc -march=systemz | grep llihf | count 1
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define i64 @foo() {
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define i64 @foo1() {
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entry:
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ret i64 0
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ret i64 1
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}
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define i64 @foo2() {
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entry:
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ret i64 65535
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}
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define i64 @foo3() {
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entry:
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ret i64 131072
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}
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define i64 @foo4() {
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entry:
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ret i64 8589934592
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}
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define i64 @foo5() {
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entry:
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ret i64 562949953421312
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}
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define i64 @foo6() {
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entry:
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ret i64 65537
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}
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define i64 @foo7() {
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entry:
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ret i64 4294967295
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}
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define i64 @foo8() {
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entry:
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ret i64 281483566645248
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}
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