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[Power9] Implement new vsx instructions: quad-precision move, fp-arithmetic
This change implements the following vsx instructions:
- quad-precision move
xscpsgnqp, xsabsqp, xsnegqp, xsnabsqp
- quad-precision fp-arithmetic
xsaddqp(o) xsdivqp(o) xsmulqp(o) xssqrtqp(o) xssubqp(o)
xsmaddqp(o) xsmsubqp(o) xsnmaddqp(o) xsnmsubqp(o)
22 instructions
Thanks Nemanja and Kit for careful review and invaluable discussion!
Reviewers: hal, nemanja, kbarton, tjablin, amehsan
http://reviews.llvm.org/D16110
llvm-svn: 264565
This commit is contained in:
Chuang-Yu Cheng
parent
fc74c1202b
commit
f63e6b8f62
@ -1819,6 +1819,55 @@ let Predicates = [HasP9Vector] in {
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: XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB),
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!strconcat(opc, " $XT, $XA, $XB"), itin, pattern>;
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// [PO VRT VRA VRB XO /]
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class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
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list<dag> pattern>
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: XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB),
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!strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>;
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// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
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class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc,
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list<dag> pattern>
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: X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isDOT;
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//===--------------------------------------------------------------------===//
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// Quad-Precision Scalar Move Instructions:
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// Copy Sign
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def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp", []>;
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// Absolute/Negative-Absolute/Negate
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def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp" , []>;
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def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp", []>;
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def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp" , []>;
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//===--------------------------------------------------------------------===//
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// Quad-Precision Scalar Floating-Point Arithmetic Instructions:
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// Add/Divide/Multiply/Subtract
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def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp" , []>;
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def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo", []>;
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def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp" , []>;
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def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo", []>;
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def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp" , []>;
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def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo", []>;
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def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" , []>;
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def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo", []>;
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// Square-Root
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def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp" , []>;
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def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", []>;
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// (Negative) Multiply-{Add/Subtract}
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def XSMADDQP : X_VT5_VA5_VB5 <63, 388, "xsmaddqp" , []>;
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def XSMADDQPO : X_VT5_VA5_VB5_Ro<63, 388, "xsmaddqpo" , []>;
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def XSMSUBQP : X_VT5_VA5_VB5 <63, 420, "xsmsubqp" , []>;
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def XSMSUBQPO : X_VT5_VA5_VB5_Ro<63, 420, "xsmsubqpo" , []>;
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def XSNMADDQP : X_VT5_VA5_VB5 <63, 452, "xsnmaddqp" , []>;
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def XSNMADDQPO: X_VT5_VA5_VB5_Ro<63, 452, "xsnmaddqpo", []>;
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def XSNMSUBQP : X_VT5_VA5_VB5 <63, 484, "xsnmsubqp" , []>;
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def XSNMSUBQPO: X_VT5_VA5_VB5_Ro<63, 484, "xsnmsubqpo", []>;
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//===--------------------------------------------------------------------===//
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// Quad/Double-Precision Compare Instructions:
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@ -141,6 +141,128 @@ Altivec:
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VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128>;
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VSX:
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- QP Copy Sign: xscpsgnqp
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. Similar to xscpsgndp
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. (set f128:$vT, (fcopysign f128:$vB, f128:$vA)
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- QP Absolute/Negative-Absolute/Negate: xsabsqp xsnabsqp xsnegqp
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. Similar to xsabsdp/xsnabsdp/xsnegdp
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. (set f128:$vT, (fabs f128:$vB)) // xsabsqp
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(set f128:$vT, (fneg (fabs f128:$vB))) // xsnabsqp
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(set f128:$vT, (fneg f128:$vB)) // xsnegqp
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- QP Add/Divide/Multiply/Subtract/Square-Root:
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xsaddqp xsdivqp xsmulqp xssubqp xssqrtqp
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. Similar to xsadddp
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. isCommutable = 1
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(set f128:$vT, (fadd f128:$vA, f128:$vB)) // xsaddqp
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(set f128:$vT, (fmul f128:$vA, f128:$vB)) // xsmulqp
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. isCommutable = 0
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(set f128:$vT, (fdiv f128:$vA, f128:$vB)) // xsdivqp
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(set f128:$vT, (fsub f128:$vA, f128:$vB)) // xssubqp
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(set f128:$vT, (fsqrt f128:$vB))) // xssqrtqp
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- Round to Odd of QP Add/Divide/Multiply/Subtract/Square-Root:
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xsaddqpo xsdivqpo xsmulqpo xssubqpo xssqrtqpo
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. Similar to xsrsqrtedp??
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def XSRSQRTEDP : XX2Form<60, 74,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xsrsqrtedp $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
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. Define DAG Node in PPCInstrInfo.td:
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def PPCfaddrto: SDNode<"PPCISD::FADDRTO", SDTFPBinOp, []>;
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def PPCfdivrto: SDNode<"PPCISD::FDIVRTO", SDTFPBinOp, []>;
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def PPCfmulrto: SDNode<"PPCISD::FMULRTO", SDTFPBinOp, []>;
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def PPCfsubrto: SDNode<"PPCISD::FSUBRTO", SDTFPBinOp, []>;
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def PPCfsqrtrto: SDNode<"PPCISD::FSQRTRTO", SDTFPUnaryOp, []>;
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DAG patterns of each instruction (PPCInstrVSX.td):
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. isCommutable = 1
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(set f128:$vT, (PPCfaddrto f128:$vA, f128:$vB)) // xsaddqpo
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(set f128:$vT, (PPCfmulrto f128:$vA, f128:$vB)) // xsmulqpo
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. isCommutable = 0
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(set f128:$vT, (PPCfdivrto f128:$vA, f128:$vB)) // xsdivqpo
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(set f128:$vT, (PPCfsubrto f128:$vA, f128:$vB)) // xssubqpo
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(set f128:$vT, (PPCfsqrtrto f128:$vB)) // xssqrtqpo
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- QP (Negative) Multiply-{Add/Subtract}: xsmaddqp xsmsubqp xsnmaddqp xsnmsubqp
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. Ref: xsmaddadp/xsmsubadp/xsnmaddadp/xsnmsubadp
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. isCommutable = 1
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// xsmaddqp
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[(set f128:$vT, (fma f128:$vA, f128:$vB, f128:$vTi))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsmsubqp
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[(set f128:$vT, (fma f128:$vA, f128:$vB, (fneg f128:$vTi)))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsnmaddqp
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[(set f128:$vT, (fneg (fma f128:$vA, f128:$vB, f128:$vTi)))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsnmsubqp
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[(set f128:$vT, (fneg (fma f128:$vA, f128:$vB, (fneg f128:$vTi))))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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- Round to Odd of QP (Negative) Multiply-{Add/Subtract}:
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xsmaddqpo xsmsubqpo xsnmaddqpo xsnmsubqpo
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. Similar to xsrsqrtedp??
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. Define DAG Node in PPCInstrInfo.td:
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def PPCfmarto: SDNode<"PPCISD::FMARTO", SDTFPTernaryOp, []>;
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It looks like we only need to define "PPCfmarto" for these instructions,
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because according to PowerISA_V3.0, these instructions perform RTO on
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fma's result:
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xsmaddqp(o)
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v ← bfp_MULTIPLY_ADD(src1, src3, src2)
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rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
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result ← bfp_CONVERT_TO_BFP128(rnd)
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xsmsubqp(o)
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v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
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rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
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result ← bfp_CONVERT_TO_BFP128(rnd)
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xsnmaddqp(o)
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v ← bfp_MULTIPLY_ADD(src1,src3,src2)
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rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v))
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result ← bfp_CONVERT_TO_BFP128(rnd)
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xsnmsubqp(o)
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v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
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rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v))
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result ← bfp_CONVERT_TO_BFP128(rnd)
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DAG patterns of each instruction (PPCInstrVSX.td):
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. isCommutable = 1
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// xsmaddqpo
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[(set f128:$vT, (PPCfmarto f128:$vA, f128:$vB, f128:$vTi))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsmsubqpo
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[(set f128:$vT, (PPCfmarto f128:$vA, f128:$vB, (fneg f128:$vTi)))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsnmaddqpo
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[(set f128:$vT, (fneg (PPCfmarto f128:$vA, f128:$vB, f128:$vTi)))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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// xsnmsubqpo
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[(set f128:$vT, (fneg (PPCfmarto f128:$vA, f128:$vB, (fneg f128:$vTi))))]>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
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AltVSXFMARel;
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- QP Compare Ordered/Unordered: xscmpoqp xscmpuqp
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. ref: XSCMPUDP
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@ -542,6 +542,72 @@
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# Power9 Instructions:
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# CHECK: xscpsgnqp 7, 31, 27
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0xfc 0xff 0xd8 0xc8
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# CHECK: xsabsqp 7, 27
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0xfc 0xe0 0xde 0x48
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# CHECK: xsnegqp 7, 27
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0xfc 0xf0 0xde 0x48
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# CHECK: xsnabsqp 7, 27
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0xfc 0xe8 0xde 0x48
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# CHECK: xsaddqp 7, 31, 27
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0xfc 0xff 0xd8 0x08
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# CHECK: xsaddqpo 7, 31, 27
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0xfc 0xff 0xd8 0x09
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# CHECK: xsdivqp 7, 31, 27
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0xfc 0xff 0xdc 0x48
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# CHECK: xsdivqpo 7, 31, 27
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0xfc 0xff 0xdc 0x49
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# CHECK: xsmulqp 7, 31, 27
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0xfc 0xff 0xd8 0x48
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# CHECK: xsmulqpo 7, 31, 27
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0xfc 0xff 0xd8 0x49
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# CHECK: xssqrtqp 7, 31
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0xfc 0xfb 0xfe 0x48
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# CHECK: xssqrtqpo 7, 31
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0xfc 0xfb 0xfe 0x49
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# CHECK: xssubqp 7, 31, 27
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0xfc 0xff 0xdc 0x08
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# CHECK: xssubqpo 7, 31, 27
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0xfc 0xff 0xdc 0x09
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# CHECK: xsmaddqp 7, 31, 27
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0xfc 0xff 0xdb 0x08
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# CHECK: xsmaddqpo 7, 31, 27
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0xfc 0xff 0xdb 0x09
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# CHECK: xsmsubqp 7, 31, 27
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0xfc 0xff 0xdb 0x48
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# CHECK: xsmsubqpo 7, 31, 27
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0xfc 0xff 0xdb 0x49
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# CHECK: xsnmaddqp 7, 31, 27
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0xfc 0xff 0xdb 0x88
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# CHECK: xsnmaddqpo 7, 31, 27
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0xfc 0xff 0xdb 0x89
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# CHECK: xsnmsubqp 7, 31, 27
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0xfc 0xff 0xdb 0xc8
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# CHECK: xsnmsubqpo 7, 31, 27
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0xfc 0xff 0xdb 0xc9
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# CHECK: xscmpoqp 6, 31, 27
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0xff 0x1f 0xd9 0x08
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@ -550,6 +550,80 @@
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# Power9 Instructions:
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# Copy Sign
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# CHECK-BE: xscpsgnqp 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0xc8]
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# CHECK-LE: xscpsgnqp 7, 31, 27 # encoding: [0xc8,0xd8,0xff,0xfc]
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xscpsgnqp 7, 31, 27
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# Absolute/Negative Absolute/Negate
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# CHECK-BE: xsabsqp 7, 27 # encoding: [0xfc,0xe0,0xde,0x48]
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# CHECK-LE: xsabsqp 7, 27 # encoding: [0x48,0xde,0xe0,0xfc]
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xsabsqp 7, 27
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# CHECK-BE: xsnegqp 7, 27 # encoding: [0xfc,0xf0,0xde,0x48]
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# CHECK-LE: xsnegqp 7, 27 # encoding: [0x48,0xde,0xf0,0xfc]
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xsnegqp 7, 27
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# CHECK-BE: xsnabsqp 7, 27 # encoding: [0xfc,0xe8,0xde,0x48]
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# CHECK-LE: xsnabsqp 7, 27 # encoding: [0x48,0xde,0xe8,0xfc]
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xsnabsqp 7, 27
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# Add/Divide/Multiply/Square-Root/Subtract
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# CHECK-BE: xsaddqp 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0x08]
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# CHECK-LE: xsaddqp 7, 31, 27 # encoding: [0x08,0xd8,0xff,0xfc]
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xsaddqp 7, 31, 27
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# CHECK-BE: xsaddqpo 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0x09]
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# CHECK-LE: xsaddqpo 7, 31, 27 # encoding: [0x09,0xd8,0xff,0xfc]
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xsaddqpo 7, 31, 27
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# CHECK-BE: xsdivqp 7, 31, 27 # encoding: [0xfc,0xff,0xdc,0x48]
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# CHECK-LE: xsdivqp 7, 31, 27 # encoding: [0x48,0xdc,0xff,0xfc]
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xsdivqp 7, 31, 27
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# CHECK-BE: xsdivqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdc,0x49]
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# CHECK-LE: xsdivqpo 7, 31, 27 # encoding: [0x49,0xdc,0xff,0xfc]
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xsdivqpo 7, 31, 27
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# CHECK-BE: xsmulqp 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0x48]
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# CHECK-LE: xsmulqp 7, 31, 27 # encoding: [0x48,0xd8,0xff,0xfc]
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xsmulqp 7, 31, 27
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# CHECK-BE: xsmulqpo 7, 31, 27 # encoding: [0xfc,0xff,0xd8,0x49]
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# CHECK-LE: xsmulqpo 7, 31, 27 # encoding: [0x49,0xd8,0xff,0xfc]
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xsmulqpo 7, 31, 27
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# CHECK-BE: xssqrtqp 7, 31 # encoding: [0xfc,0xfb,0xfe,0x48]
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# CHECK-LE: xssqrtqp 7, 31 # encoding: [0x48,0xfe,0xfb,0xfc]
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xssqrtqp 7, 31
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# CHECK-BE: xssqrtqpo 7, 31 # encoding: [0xfc,0xfb,0xfe,0x49]
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# CHECK-LE: xssqrtqpo 7, 31 # encoding: [0x49,0xfe,0xfb,0xfc]
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xssqrtqpo 7, 31
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# CHECK-BE: xssubqp 7, 31, 27 # encoding: [0xfc,0xff,0xdc,0x08]
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# CHECK-LE: xssubqp 7, 31, 27 # encoding: [0x08,0xdc,0xff,0xfc]
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xssubqp 7, 31, 27
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# CHECK-BE: xssubqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdc,0x09]
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# CHECK-LE: xssubqpo 7, 31, 27 # encoding: [0x09,0xdc,0xff,0xfc]
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xssubqpo 7, 31, 27
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# (Negative) Multiply-Add/Subtract
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# CHECK-BE: xsmaddqp 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x08]
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# CHECK-LE: xsmaddqp 7, 31, 27 # encoding: [0x08,0xdb,0xff,0xfc]
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xsmaddqp 7, 31, 27
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# CHECK-BE: xsmaddqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x09]
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# CHECK-LE: xsmaddqpo 7, 31, 27 # encoding: [0x09,0xdb,0xff,0xfc]
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xsmaddqpo 7, 31, 27
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# CHECK-BE: xsmsubqp 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x48]
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# CHECK-LE: xsmsubqp 7, 31, 27 # encoding: [0x48,0xdb,0xff,0xfc]
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xsmsubqp 7, 31, 27
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# CHECK-BE: xsmsubqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x49]
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# CHECK-LE: xsmsubqpo 7, 31, 27 # encoding: [0x49,0xdb,0xff,0xfc]
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xsmsubqpo 7, 31, 27
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# CHECK-BE: xsnmaddqp 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x88]
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# CHECK-LE: xsnmaddqp 7, 31, 27 # encoding: [0x88,0xdb,0xff,0xfc]
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||||
xsnmaddqp 7, 31, 27
|
||||
# CHECK-BE: xsnmaddqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0x89]
|
||||
# CHECK-LE: xsnmaddqpo 7, 31, 27 # encoding: [0x89,0xdb,0xff,0xfc]
|
||||
xsnmaddqpo 7, 31, 27
|
||||
# CHECK-BE: xsnmsubqp 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0xc8]
|
||||
# CHECK-LE: xsnmsubqp 7, 31, 27 # encoding: [0xc8,0xdb,0xff,0xfc]
|
||||
xsnmsubqp 7, 31, 27
|
||||
# CHECK-BE: xsnmsubqpo 7, 31, 27 # encoding: [0xfc,0xff,0xdb,0xc9]
|
||||
# CHECK-LE: xsnmsubqpo 7, 31, 27 # encoding: [0xc9,0xdb,0xff,0xfc]
|
||||
xsnmsubqpo 7, 31, 27
|
||||
|
||||
# Compare Ordered/Unordered
|
||||
# CHECK-BE: xscmpoqp 6, 31, 27 # encoding: [0xff,0x1f,0xd9,0x08]
|
||||
# CHECK-LE: xscmpoqp 6, 31, 27 # encoding: [0x08,0xd9,0x1f,0xff]
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user