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[TableGen] Report an error instead of asserting

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This gives a nice error if you accidentally try to use an empty list for
the RegTypes of a RegisterClass.

Differential Revision: https://reviews.llvm.org/D78285
This commit is contained in:
Jay Foad 2020-04-16 09:29:28 +01:00
parent 632293dfd7
commit f65d86c32b
2 changed files with 9 additions and 1 deletions
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7
test/TableGen/RegisterClass.td Normal file
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@ -0,0 +1,7 @@
// RUN: not llvm-tblgen -gen-register-bank -I %p/../../include %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
def MyTarget : Target;
def R0 : Register<"r0">;
def ClassA : RegisterClass<"MyTarget", [], 32, (add R0)>; // CHECK: [[@LINE]]:1: error: RegTypes list must not be empty!

3
utils/TableGen/CodeGenRegisters.cpp
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@ -743,6 +743,8 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1) {
GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
if (TypeList.empty())
PrintFatalError(R->getLoc(), "RegTypes list must not be empty!");
for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
Record *Type = TypeList[i];
if (!Type->isSubClassOf("ValueType"))
@ -751,7 +753,6 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
"' does not derive from the ValueType class!");
VTs.push_back(getValueTypeByHwMode(Type, RegBank.getHwModes()));
}
assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
// Allocation order 0 is the full set. AltOrders provides others.
const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);