mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
- Improved v8i16 shuffle lowering. It now uses pshuflw and pshufhw as much as
possible before resorting to pextrw and pinsrw. - Better codegen for v4i32 shuffles masquerading as v8i16 or v16i8 shuffles. - Improves (i16 extract_vector_element 0) codegen by recognizing (i32 extract_vector_element 0) does not require a pextrw. llvm-svn: 44836
This commit is contained in:
Evan Cheng
parent
8b194d1718
commit
f6c2838f36
@ -23,6 +23,7 @@
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#include "llvm/GlobalVariable.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/Analysis/ScalarEvolutionExpressions.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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@ -35,6 +36,7 @@
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ParameterAttributes.h"
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using namespace llvm;
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@ -2714,7 +2716,7 @@ static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val > 4)
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if (Val >= 4)
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return false;
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}
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@ -3130,6 +3132,8 @@ static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
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return V;
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}
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/// is4WideVector - Returns true if the specific v8i16 or v16i8 vector is
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/// actually just a 4 wide vector. e.g. <a, a, y, y, d, d, x, x>
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SDOperand
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X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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// All zero's are handled with pxor, all one's are handled with pcmpeqd.
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@ -3154,7 +3158,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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unsigned NumNonZero = 0;
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unsigned NonZeros = 0;
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unsigned NumNonZeroImms = 0;
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std::set<SDOperand> Values;
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SmallSet<SDOperand, 8> Values;
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for (unsigned i = 0; i < NumElems; ++i) {
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SDOperand Elt = Op.getOperand(i);
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if (Elt.getOpcode() != ISD::UNDEF) {
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@ -3314,59 +3318,179 @@ static
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SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
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SDOperand PermMask, SelectionDAG &DAG,
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TargetLowering &TLI) {
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SDOperand NewV;
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MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8);
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MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
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if (isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
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// Handle v8i16 shuffle high / low shuffle node pair.
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SmallVector<SDOperand, 8> MaskVec;
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for (unsigned i = 0; i != 4; ++i)
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MaskVec.push_back(PermMask.getOperand(i));
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for (unsigned i = 4; i != 8; ++i)
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MaskVec.push_back(DAG.getConstant(i, MaskEVT));
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
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V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V2, Mask);
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MaskVec.clear();
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for (unsigned i = 0; i != 4; ++i)
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MaskVec.push_back(DAG.getConstant(i, MaskEVT));
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for (unsigned i = 4; i != 8; ++i)
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MaskVec.push_back(PermMask.getOperand(i));
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Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V2, Mask);
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MVT::ValueType PtrVT = TLI.getPointerTy();
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SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
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PermMask.Val->op_end());
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// First record which half of which vector the low elements come from.
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SmallVector<unsigned, 4> LowQuad(4);
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for (unsigned i = 0; i < 4; ++i) {
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SDOperand Elt = MaskElts[i];
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if (Elt.getOpcode() == ISD::UNDEF)
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continue;
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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int QuadIdx = EltIdx / 4;
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++LowQuad[QuadIdx];
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}
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int BestLowQuad = -1;
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unsigned MaxQuad = 1;
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for (unsigned i = 0; i < 4; ++i) {
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if (LowQuad[i] > MaxQuad) {
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BestLowQuad = i;
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MaxQuad = LowQuad[i];
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}
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}
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// Lower than into extracts and inserts but try to do as few as possible.
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// Record which half of which vector the high elements come from.
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SmallVector<unsigned, 4> HighQuad(4);
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for (unsigned i = 4; i < 8; ++i) {
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SDOperand Elt = MaskElts[i];
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if (Elt.getOpcode() == ISD::UNDEF)
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continue;
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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int QuadIdx = EltIdx / 4;
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++HighQuad[QuadIdx];
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}
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int BestHighQuad = -1;
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MaxQuad = 1;
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for (unsigned i = 0; i < 4; ++i) {
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if (HighQuad[i] > MaxQuad) {
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BestHighQuad = i;
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MaxQuad = HighQuad[i];
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}
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}
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// If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
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if (BestLowQuad != -1 || BestHighQuad != -1) {
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// First sort the 4 chunks in order using shufpd.
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SmallVector<SDOperand, 8> MaskVec;
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if (BestLowQuad != -1)
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MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
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else
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MaskVec.push_back(DAG.getConstant(0, MVT::i32));
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if (BestHighQuad != -1)
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MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
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else
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MaskVec.push_back(DAG.getConstant(1, MVT::i32));
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SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
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NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
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DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
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DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
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NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
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// Now sort high and low parts separately.
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BitVector InOrder(8);
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if (BestLowQuad != -1) {
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// Sort lower half in order using PSHUFLW.
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MaskVec.clear();
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bool AnyOutOrder = false;
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for (unsigned i = 0; i != 4; ++i) {
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SDOperand Elt = MaskElts[i];
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if (Elt.getOpcode() == ISD::UNDEF) {
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MaskVec.push_back(Elt);
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InOrder.set(i);
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} else {
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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if (EltIdx != i)
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AnyOutOrder = true;
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MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
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// If this element is in the right place after this shuffle, then
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// remember it.
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if ((int)(EltIdx / 4) == BestLowQuad)
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InOrder.set(i);
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}
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}
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if (AnyOutOrder) {
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for (unsigned i = 4; i != 8; ++i)
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MaskVec.push_back(DAG.getConstant(i, MaskEVT));
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
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NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
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}
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}
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if (BestHighQuad != -1) {
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// Sort high half in order using PSHUFHW if possible.
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MaskVec.clear();
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for (unsigned i = 0; i != 4; ++i)
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MaskVec.push_back(DAG.getConstant(i, MaskEVT));
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bool AnyOutOrder = false;
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for (unsigned i = 4; i != 8; ++i) {
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SDOperand Elt = MaskElts[i];
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if (Elt.getOpcode() == ISD::UNDEF) {
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MaskVec.push_back(Elt);
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InOrder.set(i);
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} else {
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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if (EltIdx != i)
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AnyOutOrder = true;
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MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
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// If this element is in the right place after this shuffle, then
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// remember it.
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if ((int)(EltIdx / 4) == BestHighQuad)
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InOrder.set(i);
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}
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}
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if (AnyOutOrder) {
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
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NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
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}
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}
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// The other elements are put in the right place using pextrw and pinsrw.
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for (unsigned i = 0; i != 8; ++i) {
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if (InOrder[i])
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continue;
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SDOperand Elt = MaskElts[i];
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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if (EltIdx == i)
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continue;
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SDOperand ExtOp = (EltIdx < 8)
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? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
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DAG.getConstant(EltIdx, PtrVT))
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: DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
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DAG.getConstant(EltIdx - 8, PtrVT));
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NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
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DAG.getConstant(i, PtrVT));
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}
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return NewV;
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}
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// PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
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///as few as possible.
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// First, let's find out how many elements are already in the right order.
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unsigned V1InOrder = 0;
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unsigned V1FromV1 = 0;
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unsigned V2InOrder = 0;
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unsigned V2FromV2 = 0;
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SmallVector<unsigned, 8> V1Elts;
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SmallVector<unsigned, 8> V2Elts;
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SmallVector<SDOperand, 8> V1Elts;
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SmallVector<SDOperand, 8> V2Elts;
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for (unsigned i = 0; i < 8; ++i) {
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SDOperand Elt = PermMask.getOperand(i);
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SDOperand Elt = MaskElts[i];
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if (Elt.getOpcode() == ISD::UNDEF) {
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V1Elts.push_back(i);
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V2Elts.push_back(i);
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V1Elts.push_back(Elt);
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V2Elts.push_back(Elt);
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++V1InOrder;
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++V2InOrder;
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continue;
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}
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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if (EltIdx == i) {
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V1Elts.push_back(Elt);
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V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
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++V1InOrder;
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} else if (EltIdx == i+8) {
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V1Elts.push_back(Elt);
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V2Elts.push_back(DAG.getConstant(i, MaskEVT));
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++V2InOrder;
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} else if (EltIdx < 8) {
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V1Elts.push_back(Elt);
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++V1FromV1;
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} else {
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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if (EltIdx == i) {
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V1Elts.push_back(i);
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V2Elts.push_back(i+8);
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++V1InOrder;
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} else if (EltIdx == i+8) {
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V1Elts.push_back(i+8);
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V2Elts.push_back(i);
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++V2InOrder;
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} else {
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V1Elts.push_back(EltIdx);
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V2Elts.push_back(EltIdx);
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if (EltIdx < 8)
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++V1FromV1;
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else
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++V2FromV2;
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}
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V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
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++V2FromV2;
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}
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}
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@ -3377,33 +3501,92 @@ SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
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std::swap(V1FromV1, V2FromV2);
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}
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MVT::ValueType PtrVT = TLI.getPointerTy();
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if (V1FromV1) {
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// If there are elements that are from V1 but out of place,
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// then first sort them in place
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SmallVector<SDOperand, 8> MaskVec;
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for (unsigned i = 0; i < 8; ++i) {
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unsigned EltIdx = V1Elts[i];
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if (EltIdx >= 8)
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MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
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else
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MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
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if ((V1FromV1 + V1InOrder) != 8) {
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// Some elements are from V2.
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if (V1FromV1) {
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// If there are elements that are from V1 but out of place,
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// then first sort them in place
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SmallVector<SDOperand, 8> MaskVec;
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for (unsigned i = 0; i < 8; ++i) {
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SDOperand Elt = V1Elts[i];
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if (Elt.getOpcode() == ISD::UNDEF) {
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MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
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continue;
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}
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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if (EltIdx >= 8)
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MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
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else
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MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
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}
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
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V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
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}
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
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V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
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NewV = V1;
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for (unsigned i = 0; i < 8; ++i) {
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SDOperand Elt = V1Elts[i];
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if (Elt.getOpcode() == ISD::UNDEF)
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continue;
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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if (EltIdx < 8)
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continue;
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SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
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DAG.getConstant(EltIdx - 8, PtrVT));
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NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
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DAG.getConstant(i, PtrVT));
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}
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return NewV;
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} else {
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// All elements are from V1.
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NewV = V1;
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for (unsigned i = 0; i < 8; ++i) {
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SDOperand Elt = V1Elts[i];
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if (Elt.getOpcode() == ISD::UNDEF)
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continue;
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
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DAG.getConstant(EltIdx, PtrVT));
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NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
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DAG.getConstant(i, PtrVT));
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}
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return NewV;
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}
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}
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/// RewriteAs4WideShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
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/// ones if possible. This can be done when every pair / quad of shuffle mask
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/// elements point to elements in the right sequence. e.g.
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/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
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static
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SDOperand RewriteAs4WideShuffle(SDOperand V1, SDOperand V2,
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SDOperand PermMask, SelectionDAG &DAG,
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TargetLowering &TLI) {
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unsigned NumElems = PermMask.getNumOperands();
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unsigned Scale = NumElems / 4;
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SmallVector<SDOperand, 4> MaskVec;
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for (unsigned i = 0; i < NumElems; i += Scale) {
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unsigned StartIdx = ~0U;
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for (unsigned j = 0; j < Scale; ++j) {
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SDOperand Elt = PermMask.getOperand(i+j);
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if (Elt.getOpcode() == ISD::UNDEF)
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continue;
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unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
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if (StartIdx == ~0U)
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StartIdx = EltIdx - (EltIdx % Scale);
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if (EltIdx != StartIdx + j)
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return SDOperand();
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}
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if (StartIdx == ~0U)
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MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
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else
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MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
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}
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// Now let's insert elements from the other vector.
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for (unsigned i = 0; i < 8; ++i) {
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unsigned EltIdx = V1Elts[i];
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if (EltIdx < 8)
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continue;
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SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
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DAG.getConstant(EltIdx - 8, PtrVT));
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V1 = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V1, ExtOp,
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DAG.getConstant(i, PtrVT));
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}
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return V1;
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V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
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V2 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V2);
|
||||
return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1, V2,
|
||||
DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0],4));
|
||||
}
|
||||
|
||||
SDOperand
|
||||
@ -3544,18 +3727,31 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
|
||||
}
|
||||
}
|
||||
|
||||
// Handle v8i16 specifically since SSE can do byte extraction and insertion.
|
||||
if (VT == MVT::v8i16)
|
||||
return LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
|
||||
// If the shuffle can be rewritten as a 4 wide shuffle, then do it!
|
||||
if (VT == MVT::v8i16 || VT == MVT::v16i8) {
|
||||
SDOperand NewOp = RewriteAs4WideShuffle(V1, V2, PermMask, DAG, *this);
|
||||
if (NewOp.Val)
|
||||
return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
|
||||
}
|
||||
|
||||
if (NumElems == 4 && MVT::getSizeInBits(VT) != 64) {
|
||||
// Handle v8i16 specifically since SSE can do byte extraction and insertion.
|
||||
if (VT == MVT::v8i16) {
|
||||
SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
|
||||
if (NewOp.Val)
|
||||
return NewOp;
|
||||
}
|
||||
|
||||
// Handle all 4 wide cases with a number of shuffles.
|
||||
if (NumElems == 4 && MVT::getSizeInBits(VT) != 64) {
|
||||
// Don't do this for MMX.
|
||||
MVT::ValueType MaskVT = PermMask.getValueType();
|
||||
MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
|
||||
SmallVector<std::pair<int, int>, 8> Locs;
|
||||
Locs.reserve(NumElems);
|
||||
SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
|
||||
SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
|
||||
SmallVector<SDOperand, 8> Mask1(NumElems,
|
||||
DAG.getNode(ISD::UNDEF, MaskEVT));
|
||||
SmallVector<SDOperand, 8> Mask2(NumElems,
|
||||
DAG.getNode(ISD::UNDEF, MaskEVT));
|
||||
unsigned NumHi = 0;
|
||||
unsigned NumLo = 0;
|
||||
// If no more than two elements come from either vector. This can be
|
||||
@ -3661,6 +3857,13 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||
MVT::ValueType VT = Op.getValueType();
|
||||
// TODO: handle v16i8.
|
||||
if (MVT::getSizeInBits(VT) == 16) {
|
||||
SDOperand Vec = Op.getOperand(0);
|
||||
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
||||
if (Idx == 0)
|
||||
return DAG.getNode(ISD::TRUNCATE, MVT::i16,
|
||||
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
|
||||
DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
|
||||
Op.getOperand(1)));
|
||||
// Transform it so it match pextrw which produces a 32-bit result.
|
||||
MVT::ValueType EVT = (MVT::ValueType)(VT+1);
|
||||
SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
|
||||
@ -3669,7 +3872,6 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||
DAG.getValueType(VT));
|
||||
return DAG.getNode(ISD::TRUNCATE, VT, Assert);
|
||||
} else if (MVT::getSizeInBits(VT) == 32) {
|
||||
SDOperand Vec = Op.getOperand(0);
|
||||
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
||||
if (Idx == 0)
|
||||
return Op;
|
||||
@ -3686,12 +3888,12 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||
push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
|
||||
SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
|
||||
&IdxVec[0], IdxVec.size());
|
||||
SDOperand Vec = Op.getOperand(0);
|
||||
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
|
||||
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
|
||||
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
|
||||
DAG.getConstant(0, getPointerTy()));
|
||||
} else if (MVT::getSizeInBits(VT) == 64) {
|
||||
SDOperand Vec = Op.getOperand(0);
|
||||
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
||||
if (Idx == 0)
|
||||
return Op;
|
||||
@ -3706,6 +3908,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||
push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
|
||||
SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
|
||||
&IdxVec[0], IdxVec.size());
|
||||
SDOperand Vec = Op.getOperand(0);
|
||||
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
|
||||
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
|
||||
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
|
||||
|
||||
@ -1,37 +1,28 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep punpck
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pextrw | count 7
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pinsrw | count 7
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshuf | count 2
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pextrw | count 4
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pinsrw | count 6
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshuflw | count 3
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | count 2
|
||||
|
||||
define void @t1(<8 x i16>* %res, <8 x i16>* %A, <8 x i16>* %B) {
|
||||
define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) {
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i16>* %B
|
||||
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
|
||||
store <8 x i16> %tmp3, <8 x i16>* %res
|
||||
ret void
|
||||
ret <8 x i16> %tmp3
|
||||
}
|
||||
|
||||
define void @t2(<8 x i16>* %res, <8 x i16>* %A, <8 x i16>* %B) {
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i16>* %B
|
||||
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7 >
|
||||
store <8 x i16> %tmp3, <8 x i16>* %res
|
||||
ret void
|
||||
define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) {
|
||||
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
|
||||
ret <8 x i16> %tmp
|
||||
}
|
||||
|
||||
define void @t3(<8 x i16>* %res, <8 x i16>* %A, <8 x i16>* %B) {
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i16>* %B
|
||||
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 >
|
||||
store <8 x i16> %tmp3, <8 x i16>* %res
|
||||
ret void
|
||||
define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) {
|
||||
%tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 >
|
||||
ret <8 x i16> %tmp
|
||||
}
|
||||
|
||||
define void @t4(<8 x i16>* %res, <8 x i16>* %A, <8 x i16>* %B) {
|
||||
%tmp1 = load <8 x i16>* %A
|
||||
%tmp2 = load <8 x i16>* %B
|
||||
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
|
||||
store <8 x i16> %tmp3, <8 x i16>* %res
|
||||
ret void
|
||||
define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) {
|
||||
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 >
|
||||
ret <8 x i16> %tmp
|
||||
}
|
||||
|
||||
21
test/CodeGen/X86/vec_shuffle-13.ll
Normal file
21
test/CodeGen/X86/vec_shuffle-13.ll
Normal file
@ -0,0 +1,21 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movlhps | count 1
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movss | count 1
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufd | count 1
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshuflw | count 1
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | count 1
|
||||
|
||||
define <8 x i16> @t1(<8 x i16> %A, <8 x i16> %B) {
|
||||
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 0, i32 1, i32 10, i32 11, i32 2, i32 3 >
|
||||
ret <8 x i16> %tmp
|
||||
}
|
||||
|
||||
define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) {
|
||||
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
|
||||
ret <8 x i16> %tmp
|
||||
}
|
||||
|
||||
define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) {
|
||||
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 0, i32 3, i32 2, i32 4, i32 6, i32 4, i32 7 >
|
||||
ret <8 x i16> %tmp
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user