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[RISCV] Reuse existing SDLoc and XLenVT in the switch in RISCVISelDAGToDAG::Select. NFC

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A SDLoc and XLenVT were already created above the switch.
This commit is contained in:
Craig Topper 2021-02-24 21:38:51 -08:00
parent c85460437c
commit f70f9b8216
1 changed files with 4 additions and 11 deletions
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15
lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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@ -435,7 +435,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
uint64_t Mask = N0.getConstantOperandVal(1);
Mask |= maskTrailingOnes<uint64_t>(ShAmt);
if (Mask == 0xffff) {
SDLoc DL(Node);
unsigned SLLOpc = Subtarget->is64Bit() ? RISCV::SLLIW : RISCV::SLLI;
unsigned SRLOpc = Subtarget->is64Bit() ? RISCV::SRLIW : RISCV::SRLI;
SDNode *SLLI =
@ -609,7 +608,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
bool IsOrdered = IntNo == Intrinsic::riscv_vloxei ||
IntNo == Intrinsic::riscv_vloxei_mask;
SDLoc DL(Node);
MVT VT = Node->getSimpleValueType(0);
unsigned ScalarSize = VT.getScalarSizeInBits();
MVT XLenVT = Subtarget->getXLenVT();
@ -658,7 +656,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
bool IsStrided =
IntNo == Intrinsic::riscv_vlse || IntNo == Intrinsic::riscv_vlse_mask;
SDLoc DL(Node);
MVT VT = Node->getSimpleValueType(0);
unsigned ScalarSize = VT.getScalarSizeInBits();
MVT XLenVT = Subtarget->getXLenVT();
@ -698,7 +695,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
case Intrinsic::riscv_vleff_mask: {
bool IsMasked = IntNo == Intrinsic::riscv_vleff_mask;
SDLoc DL(Node);
MVT VT = Node->getSimpleValueType(0);
unsigned ScalarSize = VT.getScalarSizeInBits();
MVT XLenVT = Subtarget->getXLenVT();
@ -827,7 +823,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
bool IsOrdered = IntNo == Intrinsic::riscv_vsoxei ||
IntNo == Intrinsic::riscv_vsoxei_mask;
SDLoc DL(Node);
MVT VT = Node->getOperand(2)->getSimpleValueType(0);
unsigned ScalarSize = VT.getScalarSizeInBits();
MVT XLenVT = Subtarget->getXLenVT();
@ -875,7 +870,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
bool IsStrided =
IntNo == Intrinsic::riscv_vsse || IntNo == Intrinsic::riscv_vsse_mask;
SDLoc DL(Node);
MVT VT = Node->getOperand(2)->getSimpleValueType(0);
unsigned ScalarSize = VT.getScalarSizeInBits();
MVT XLenVT = Subtarget->getXLenVT();
@ -929,8 +923,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
SDValue SubV = Node->getOperand(1);
SDLoc DL(SubV);
auto Idx = Node->getConstantOperandVal(2);
MVT XLenVT = Subtarget->getXLenVT();
MVT SubVecVT = Node->getOperand(1).getSimpleValueType();
MVT SubVecVT = SubV.getSimpleValueType();
// TODO: This method of selecting INSERT_SUBVECTOR should work
// with any type of insertion (fixed <-> scalable) but we don't yet
@ -998,7 +991,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
case ISD::EXTRACT_SUBVECTOR: {
SDValue V = Node->getOperand(0);
auto Idx = Node->getConstantOperandVal(1);
MVT InVT = Node->getOperand(0).getSimpleValueType();
MVT InVT = V.getSimpleValueType();
SDLoc DL(V);
// TODO: This method of selecting EXTRACT_SUBVECTOR should work
@ -1028,14 +1021,14 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
InRegClassID == RISCV::VRRegClassID &&
"Unexpected subvector extraction");
SDValue RC =
CurDAG->getTargetConstant(InRegClassID, DL, Subtarget->getXLenVT());
CurDAG->getTargetConstant(InRegClassID, DL, XLenVT);
SDNode *NewNode = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
DL, VT, V, RC);
return ReplaceNode(Node, NewNode);
}
SDNode *NewNode = CurDAG->getMachineNode(
TargetOpcode::EXTRACT_SUBREG, DL, VT, V,
CurDAG->getTargetConstant(SubRegIdx, DL, Subtarget->getXLenVT()));
CurDAG->getTargetConstant(SubRegIdx, DL, XLenVT));
return ReplaceNode(Node, NewNode);
}