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[AArch64][MC] Reject "add x0, x1, w2, lsl #1" etc.

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Looks like just a minor oversight in the parsing code.

Fixes https://bugs.llvm.org/show_bug.cgi?id=41504.

Differential Revision: https://reviews.llvm.org/D60840

llvm-svn: 359855
This commit is contained in:
Eli Friedman 2019-05-03 00:59:52 +00:00
parent 7706a4c905
commit f714f84cd7
2 changed files with 11 additions and 5 deletions
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8
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -1270,9 +1270,11 @@ public:
bool isExtend64() const {
if (!isExtend())
return false;
// UXTX and SXTX require a 64-bit source register (the ExtendLSL64 class).
// Make sure the extend expects a 32-bit source register.
AArch64_AM::ShiftExtendType ET = getShiftExtendType();
return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX;
return ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB ||
ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH ||
ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW;
}
bool isExtendLSL64() const {
@ -4189,7 +4191,7 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
return Error(Loc, "expected AArch64 condition code");
case Match_AddSubRegExtendSmall:
return Error(Loc,
"expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]");
"expected '[su]xt[bhw]' with optional integer in range [0, 4]");
case Match_AddSubRegExtendLarge:
return Error(Loc,
"expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]");

8
test/MC/AArch64/basic-a64-diagnostics.s
View File

@ -8,13 +8,17 @@
// Mismatched final register and extend
add x2, x3, x5, sxtb
add x2, x4, w2, uxtx
add x2, x4, w2, lsl #3
add w5, w7, x9, sxtx
// CHECK-ERROR: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
// CHECK-ERROR: add x2, x3, x5, sxtb
// CHECK-ERROR: ^
// CHECK-ERROR: error: expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]
// CHECK-ERROR: error: expected '[su]xt[bhw]' with optional integer in range [0, 4]
// CHECK-ERROR: add x2, x4, w2, uxtx
// CHECK-ERROR: ^
// CHECK-ERROR: error: expected '[su]xt[bhw]' with optional integer in range [0, 4]
// CHECK-ERROR: add x2, x4, w2, lsl #3
// CHECK-ERROR: ^
// CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095]
// CHECK-ERROR: add w5, w7, x9, sxtx
// CHECK-ERROR: ^
@ -26,7 +30,7 @@
// CHECK-ERROR: error: expected integer shift amount
// CHECK-ERROR: add x9, x10, w11, uxtb #-1
// CHECK-ERROR: ^
// CHECK-ERROR: error: expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]
// CHECK-ERROR: error: expected '[su]xt[bhw]' with optional integer in range [0, 4]
// CHECK-ERROR: add x3, x5, w7, uxtb #5
// CHECK-ERROR: ^
// CHECK-ERROR: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]