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tidy up a few 80-column and trailing whitespace bits.

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llvm-svn: 112726
This commit is contained in:
Jim Grosbach 2010-09-01 19:16:29 +00:00
parent 988287ae88
commit f727f525cd
1 changed files with 19 additions and 16 deletions
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25
lib/CodeGen/RegAllocFast.cpp
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@ -113,9 +113,9 @@ namespace {
// Allocatable - vector of allocatable physical registers.
BitVector Allocatable;
// SkippedInstrs - Descriptors of instructions whose clobber list was ignored
// because all registers were spilled. It is still necessary to mark all the
// clobbered registers as used by the function.
// SkippedInstrs - Descriptors of instructions whose clobber list was
// ignored because all registers were spilled. It is still necessary to
// mark all the clobbered registers as used by the function.
SmallPtrSet<const TargetInstrDesc*, 4> SkippedInstrs;
// isBulkSpilling - This flag is set when LiveRegMap will be cleared
@ -796,7 +796,8 @@ void RAFast::AllocateBasicBlock() {
else {
int SS = StackSlotForVirtReg[Reg];
if (SS == -1)
MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
// We can't allocate a physreg for a DebugValue, sorry!
MO.setReg(0);
else {
// Modify DBG_VALUE now that the value is in a spill slot.
int64_t Offset = MI->getOperand(1).getImm();
@ -805,7 +806,8 @@ void RAFast::AllocateBasicBlock() {
DebugLoc DL = MI->getDebugLoc();
if (MachineInstr *NewDV =
TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
DEBUG(dbgs() << "Modifying debug info due to spill:" <<
"\t" << *MI);
MachineBasicBlock *MBB = MI->getParent();
MBB->insert(MBB->erase(MI), NewDV);
// Scan NewDV operands from the beginning.
@ -813,7 +815,8 @@ void RAFast::AllocateBasicBlock() {
ScanDbgValue = true;
break;
} else
MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
// We can't allocate a physreg for a DebugValue; sorry!
MO.setReg(0);
}
}
}
@ -876,8 +879,8 @@ void RAFast::AllocateBasicBlock() {
// operands. If there are also physical defs, these registers must avoid
// both physical defs and uses, making them more constrained than normal
// operands.
// Similarly, if there are multiple defs and tied operands, we must make sure
// the same register is allocated to uses and defs.
// Similarly, if there are multiple defs and tied operands, we must make
// sure the same register is allocated to uses and defs.
// We didn't detect inline asm tied operands above, so just make this extra
// pass for all inline asm.
if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
@ -928,9 +931,9 @@ void RAFast::AllocateBasicBlock() {
unsigned DefOpEnd = MI->getNumOperands();
if (TID.isCall()) {
// Spill all virtregs before a call. This serves two purposes: 1. If an
// exception is thrown, the landing pad is going to expect to find registers
// in their spill slots, and 2. we don't have to wade through all the
// <imp-def> operands on the call instruction.
// exception is thrown, the landing pad is going to expect to find
// registers in their spill slots, and 2. we don't have to wade through
// all the <imp-def> operands on the call instruction.
DefOpEnd = VirtOpEnd;
DEBUG(dbgs() << " Spilling remaining registers before call.\n");
spillAll(MI);