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[SPARC] Fix 8 and 16-bit atomic load and store.

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They were accidentally using the 32-bit load/store instruction for
8/16-bit operations, due to incorrect patterns

(8/16-bit cmpxchg and atomicrmw will be fixed in subsequent changes)

llvm-svn: 270486
This commit is contained in:
James Y Knight 2016-05-23 20:33:00 +00:00
parent 4a1b9faea8
commit f767eef5cb
3 changed files with 56 additions and 16 deletions
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10
lib/Target/Sparc/SparcInstr64Bit.td
View File

@ -492,7 +492,7 @@ let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
I64Regs:$swap),
"casx [$rs1], $rs2, $rd",
[(set i64:$rd,
(atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>;
(atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>;
} // Predicates = [Is64Bit], Constraints = ...
@ -501,12 +501,12 @@ let Predicates = [Is64Bit] in {
def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
// atomic_load_64 addr -> load addr
def : Pat<(i64 (atomic_load ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
def : Pat<(i64 (atomic_load ADDRri:$src)), (LDXri ADDRri:$src)>;
def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>;
// atomic_store_64 val, addr -> store val, addr
def : Pat<(atomic_store ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>;
def : Pat<(atomic_store_64 ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store_64 ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>;
} // Predicates = [Is64Bit]

24
lib/Target/Sparc/SparcInstrInfo.td
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@ -1505,7 +1505,7 @@ let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
IntRegs:$swap),
"cas [$rs1], $rs2, $rd",
[(set i32:$rd,
(atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
// CASA is supported as an instruction on some LEON3 and all LEON4 processors.
@ -1516,7 +1516,7 @@ let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
IntRegs:$swap),
"casa [$rs1] 10, $rs2, $rd",
[(set i32:$rd,
(atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
(atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
// CASA supported on some LEON3 and all LEON4 processors. Same pattern as
// CASrr, above, but with a different ASI. This version is supported for
@ -1645,13 +1645,21 @@ def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
let Predicates = [HasNoV9] in
def : Pat<(atomic_fence imm, imm), (STBAR)>;
// atomic_load_32 addr -> load addr
def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
// atomic_load addr -> load addr
def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>;
def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>;
// atomic_store_32 val, addr -> store val, addr
def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
// atomic_store val, addr -> store val, addr
def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>;
def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>;
def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
// extract_vector
def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),

38
test/CodeGen/SPARC/atomics.ll
View File

@ -1,5 +1,37 @@
; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
; CHECK-LABEL: test_atomic_i8
; CHECK: ldub [%o0]
; CHECK: membar
; CHECK: ldub [%o1]
; CHECK: membar
; CHECK: membar
; CHECK: stb {{.+}}, [%o2]
define i8 @test_atomic_i8(i8* %ptr1, i8* %ptr2, i8* %ptr3) {
entry:
%0 = load atomic i8, i8* %ptr1 acquire, align 1
%1 = load atomic i8, i8* %ptr2 acquire, align 1
%2 = add i8 %0, %1
store atomic i8 %2, i8* %ptr3 release, align 1
ret i8 %2
}
; CHECK-LABEL: test_atomic_i16
; CHECK: lduh [%o0]
; CHECK: membar
; CHECK: lduh [%o1]
; CHECK: membar
; CHECK: membar
; CHECK: sth {{.+}}, [%o2]
define i16 @test_atomic_i16(i16* %ptr1, i16* %ptr2, i16* %ptr3) {
entry:
%0 = load atomic i16, i16* %ptr1 acquire, align 2
%1 = load atomic i16, i16* %ptr2 acquire, align 2
%2 = add i16 %0, %1
store atomic i16 %2, i16* %ptr3 release, align 2
ret i16 %2
}
; CHECK-LABEL: test_atomic_i32
; CHECK: ld [%o0]
; CHECK: membar
@ -9,10 +41,10 @@
; CHECK: st {{.+}}, [%o2]
define i32 @test_atomic_i32(i32* %ptr1, i32* %ptr2, i32* %ptr3) {
entry:
%0 = load atomic i32, i32* %ptr1 acquire, align 8
%1 = load atomic i32, i32* %ptr2 acquire, align 8
%0 = load atomic i32, i32* %ptr1 acquire, align 4
%1 = load atomic i32, i32* %ptr2 acquire, align 4
%2 = add i32 %0, %1
store atomic i32 %2, i32* %ptr3 release, align 8
store atomic i32 %2, i32* %ptr3 release, align 4
ret i32 %2
}