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On ARM, alignment is in bits

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Add lr as a hard coded operand of bx

llvm-svn: 28494
This commit is contained in:
Rafael Espindola 2006-05-26 10:56:17 +00:00
parent c80154a36e
commit f7c5af4863
2 changed files with 7 additions and 2 deletions
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3
lib/Target/ARM/ARMAsmPrinter.cpp
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@ -44,6 +44,7 @@ namespace {
ZeroDirective = "\t.skip\t"; ZeroDirective = "\t.skip\t";
CommentString = "!"; CommentString = "!";
ConstantPoolSection = "\t.section \".rodata\",#alloc\n"; ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
AlignmentIsInBytes = false;
} }
/// We name each basic block in a Function with a unique number, so /// We name each basic block in a Function with a unique number, so
@ -110,7 +111,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
assert(0 && "Not implemented"); assert(0 && "Not implemented");
break; break;
} }
EmitAlignment(4, F); EmitAlignment(2, F);
O << CurrentFnName << ":\n"; O << CurrentFnName << ":\n";
// Print out code for the function. // Print out code for the function.

6
lib/Target/ARM/ARMInstrInfo.td
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@ -42,7 +42,11 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKDOWN $amt", "!ADJCALLSTACKDOWN $amt",
[(callseq_start imm:$amt)]>; [(callseq_start imm:$amt)]>;
def BX: InstARM<(ops), "bx", [(retflag)]>; //bx supports other registers as operands. So this looks like a
//hack. Maybe a ret should be expanded to a "branch lr" and bx
//declared as a regular instruction
def BX: InstARM<(ops), "bx lr", [(retflag)]>;
def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr), def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
"ldr $dst, [$addr]", "ldr $dst, [$addr]",