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legalize vbit_convert nodes whose result is a legal type.
Legalize intrinsic nodes. llvm-svn: 27036
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@ -552,6 +552,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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}
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break;
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}
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case ISD::INTRINSIC: {
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std::vector<SDOperand> Ops;
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for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
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Ops.push_back(LegalizeOp(Node->getOperand(i)));
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Result = DAG.UpdateNodeOperands(Result, Ops);
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break;
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}
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case ISD::LOCATION:
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assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
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@ -2312,6 +2320,36 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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}
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}
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break;
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case ISD::VBIT_CONVERT: {
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assert(Op.getOperand(0).getValueType() == MVT::Vector &&
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"Can only have VBIT_CONVERT where input or output is MVT::Vector!");
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// The input has to be a vector type, we have to either scalarize it, pack
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// it, or convert it based on whether the input vector type is legal.
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SDNode *InVal = Node->getOperand(0).Val;
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unsigned NumElems =
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cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
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MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
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// Figure out if there is a Packed type corresponding to this Vector
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// type. If so, convert to the packed type.
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MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
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if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
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// Turn this into a bit convert of the packed input.
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Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
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PackVectorOp(Node->getOperand(0), TVT));
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break;
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} else if (NumElems == 1) {
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// Turn this into a bit convert of the scalar input.
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Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
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PackVectorOp(Node->getOperand(0), EVT));
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break;
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} else {
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// FIXME: UNIMP! Store then reload
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assert(0 && "Cast from unsupported vector type not implemented yet!");
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}
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}
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// Conversion operators. The source and destination have different types.
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP: {
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