From f7d5e35caa1acef8241445533660260876759bea Mon Sep 17 00:00:00 2001 From: Hans Wennborg Date: Mon, 31 Aug 2015 21:10:35 +0000 Subject: [PATCH] Fix CHECK directives that weren't checking. llvm-svn: 246485 --- test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll | 9 ++++----- test/CodeGen/AMDGPU/fcmp.ll | 2 +- test/CodeGen/AMDGPU/flat-address-space.ll | 14 +++++++------- test/CodeGen/ARM/thumb_indirect_calls.ll | 5 ++--- test/CodeGen/SPARC/select-mask.ll | 2 +- test/CodeGen/WinEH/wineh-cloning.ll | 4 ++-- test/MC/AArch64/arm64-diags.s | 2 +- test/MC/Sparc/sparc-relocations.s | 10 +++++----- test/Transforms/InstSimplify/shr-nop.ll | 12 ++++++------ test/Transforms/LICM/pr23608.ll | 2 +- .../RewriteStatepointsForGC/codegen-cond.ll | 6 +++--- test/Transforms/SROA/basictest.ll | 2 +- .../Transforms/StructurizeCFG/nested-loop-order.ll | 2 +- 13 files changed, 35 insertions(+), 37 deletions(-) diff --git a/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll b/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll index 2adbcdf3795..528d2538bb4 100644 --- a/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll +++ b/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s | FileCheck %s -; CHECK: orr w0, wzr, #0x1 -; CHECK-NEXT : bl foo -; CHECK-NEXT : orr w0, wzr, #0x1 -; CHECK-NEXT : bl foo +; CHECK: orr w0, wzr, #0x1 +; CHECK-NEXT: bl foo +; CHECK-NEXT: orr w0, wzr, #0x1 +; CHECK-NEXT: bl foo target triple = "aarch64--linux-android" declare i32 @foo(i32) @@ -15,4 +15,3 @@ entry: %call1 = tail call i32 @foo(i32 1) ret i32 0 } - diff --git a/test/CodeGen/AMDGPU/fcmp.ll b/test/CodeGen/AMDGPU/fcmp.ll index 5207ab57bad..97d954fcc3c 100644 --- a/test/CodeGen/AMDGPU/fcmp.ll +++ b/test/CodeGen/AMDGPU/fcmp.ll @@ -20,7 +20,7 @@ entry: ; CHECK: {{^}}fcmp_br: ; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}} -; CHECK-NEXT {{[0-9]+(5.0}} +; CHECK-NEXT: {{[0-9]+\(5.0}} define void @fcmp_br(i32 addrspace(1)* %out, float %in) { entry: diff --git a/test/CodeGen/AMDGPU/flat-address-space.ll b/test/CodeGen/AMDGPU/flat-address-space.ll index 8ceca078f2d..571685ca6ae 100644 --- a/test/CodeGen/AMDGPU/flat-address-space.ll +++ b/test/CodeGen/AMDGPU/flat-address-space.ll @@ -83,7 +83,7 @@ define void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 { -; CHECK-LABEL @load_flat_i32: +; CHECK-LABEL: load_flat_i32: ; CHECK: flat_load_dword define void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* @@ -92,7 +92,7 @@ define void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noa ret void } -; CHECK-LABEL @load_flat_i64: +; CHECK-LABEL: load_flat_i64: ; CHECK: flat_load_dwordx2 define void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)* @@ -101,7 +101,7 @@ define void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa ret void } -; CHECK-LABEL @load_flat_v4i32: +; CHECK-LABEL: load_flat_v4i32: ; CHECK: flat_load_dwordx4 define void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)* @@ -110,7 +110,7 @@ define void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> add ret void } -; CHECK-LABEL @sextload_flat_i8: +; CHECK-LABEL: sextload_flat_i8: ; CHECK: flat_load_sbyte define void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* @@ -120,7 +120,7 @@ define void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* n ret void } -; CHECK-LABEL @zextload_flat_i8: +; CHECK-LABEL: zextload_flat_i8: ; CHECK: flat_load_ubyte define void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* @@ -130,7 +130,7 @@ define void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* n ret void } -; CHECK-LABEL @sextload_flat_i16: +; CHECK-LABEL: sextload_flat_i16: ; CHECK: flat_load_sshort define void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* @@ -140,7 +140,7 @@ define void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* ret void } -; CHECK-LABEL @zextload_flat_i16: +; CHECK-LABEL: zextload_flat_i16: ; CHECK: flat_load_ushort define void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 { %fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* diff --git a/test/CodeGen/ARM/thumb_indirect_calls.ll b/test/CodeGen/ARM/thumb_indirect_calls.ll index 9f1950c743c..67346c6fde9 100644 --- a/test/CodeGen/ARM/thumb_indirect_calls.ll +++ b/test/CodeGen/ARM/thumb_indirect_calls.ll @@ -3,7 +3,7 @@ @f = common global void (i32)* null, align 4 -; CHECK-LABEL foo: +; CHECK-LABEL: foo: define void @foo(i32 %x) { entry: %0 = load void (i32)*, void (i32)** @f, align 4 @@ -21,7 +21,7 @@ entry: ; CHECK-V5T: blx [[CALLEE]] } -; CHECK-LABEL bar: +; CHECK-LABEL: bar: define void @bar(void (i32)* nocapture %g, i32 %x, void (i32)* nocapture %h) { entry: tail call void %g(i32 %x) @@ -37,4 +37,3 @@ entry: ; CHECK-V5T: blx ; CHECK-V5T: blx } - diff --git a/test/CodeGen/SPARC/select-mask.ll b/test/CodeGen/SPARC/select-mask.ll index 12e57103594..2e69a3b9be5 100644 --- a/test/CodeGen/SPARC/select-mask.ll +++ b/test/CodeGen/SPARC/select-mask.ll @@ -4,7 +4,7 @@ ;; other than the first for SELECT. Thus, the 'trunc' got eliminated ;; as redundant. But, cmp does NOT ignore the other bits! -; CHECK-LABEL select_mask: +; CHECK-LABEL: select_mask: ; CHECK: ldub [%o0], [[R:%[goli][0-7]]] ; CHECK: and [[R]], 1, [[V:%[goli][0-7]]] ; CHECK: cmp [[V]], 0 diff --git a/test/CodeGen/WinEH/wineh-cloning.ll b/test/CodeGen/WinEH/wineh-cloning.ll index fff358b902a..39e5d40a48f 100644 --- a/test/CodeGen/WinEH/wineh-cloning.ll +++ b/test/CodeGen/WinEH/wineh-cloning.ll @@ -168,10 +168,10 @@ exit: ; CHECK: br i1 [[b_E]], label %[[left_E:[^ ]+]], label %[[right_E:[^ ]+]] ; CHECK: [[left_C]]: ; CHECK: [[y_C:%[^ ]+]] = call i32 @g() -; CHECK br label %[[looptail_C]] +; CHECK: br label %[[looptail_C]] ; CHECK: [[left_E]]: ; CHECK: [[y_E:%[^ ]+]] = call i32 @g() -; CHECK br label %[[looptail_E]] +; CHECK: br label %[[looptail_E]] ; CHECK: [[right_C]]: ; CHECK: call void @h(i32 [[x_C]]) ; CHECK: br label %[[looptail_C]] diff --git a/test/MC/AArch64/arm64-diags.s b/test/MC/AArch64/arm64-diags.s index 8fdba9f2f62..e368d50f3b2 100644 --- a/test/MC/AArch64/arm64-diags.s +++ b/test/MC/AArch64/arm64-diags.s @@ -461,7 +461,7 @@ tlbi vale3 ; CHECK-ERRORS: error: invalid operand for instruction ; CHECK-ERRORS: frsqrte.4s v0, v1, v2 -; CHECK-ERRORS ^ +; CHECK-ERRORS: ^ ; CHECK-ERRORS: error: too few operands for instruction ; CHECK-ERRORS: frsqrte.2s v0 ; CHECK-ERRORS: ^ diff --git a/test/MC/Sparc/sparc-relocations.s b/test/MC/Sparc/sparc-relocations.s index a5b7bafa4f5..58ad37e1da5 100644 --- a/test/MC/Sparc/sparc-relocations.s +++ b/test/MC/Sparc/sparc-relocations.s @@ -18,7 +18,7 @@ call foo ! CHECK: or %g1, %lo(sym), %g3 ! encoding: [0x86,0x10,0b011000AA,A] - ! CHECK-NEXT ! fixup A - offset: 0, value: %lo(sym), kind: fixup_sparc_lo10 + ! CHECK-NEXT: ! fixup A - offset: 0, value: %lo(sym), kind: fixup_sparc_lo10 or %g1, %lo(sym), %g3 ! CHECK: sethi %hi(sym), %l0 ! encoding: [0x21,0b00AAAAAA,A,A] @@ -26,15 +26,15 @@ sethi %hi(sym), %l0 ! CHECK: sethi %h44(sym), %l0 ! encoding: [0x21,0b00AAAAAA,A,A] - ! CHECK-NEXT: ! fixup A - offset: 0, value: %h44(sym), kind: fixup_sparc_h44 + ! CHECK-NEXT: ! fixup A - offset: 0, value: %h44(sym), kind: fixup_sparc_h44 sethi %h44(sym), %l0 ! CHECK: or %g1, %m44(sym), %g3 ! encoding: [0x86,0x10,0b011000AA,A] - ! CHECK-NEXT ! fixup A - offset: 0, value: %m44(sym), kind: fixup_sparc_m44 + ! CHECK-NEXT: ! fixup A - offset: 0, value: %m44(sym), kind: fixup_sparc_m44 or %g1, %m44(sym), %g3 ! CHECK: or %g1, %l44(sym), %g3 ! encoding: [0x86,0x10,0b0110AAAA,A] - ! CHECK-NEXT ! fixup A - offset: 0, value: %l44(sym), kind: fixup_sparc_l44 + ! CHECK-NEXT: ! fixup A - offset: 0, value: %l44(sym), kind: fixup_sparc_l44 or %g1, %l44(sym), %g3 ! CHECK: sethi %hh(sym), %l0 ! encoding: [0x21,0b00AAAAAA,A,A] @@ -42,5 +42,5 @@ sethi %hh(sym), %l0 ! CHECK: or %g1, %hm(sym), %g3 ! encoding: [0x86,0x10,0b011000AA,A] - ! CHECK-NEXT ! fixup A - offset: 0, value: %hm(sym), kind: fixup_sparc_hm + ! CHECK-NEXT: ! fixup A - offset: 0, value: %hm(sym), kind: fixup_sparc_hm or %g1, %hm(sym), %g3 diff --git a/test/Transforms/InstSimplify/shr-nop.ll b/test/Transforms/InstSimplify/shr-nop.ll index b0dc8731a11..edabcc314ea 100644 --- a/test/Transforms/InstSimplify/shr-nop.ll +++ b/test/Transforms/InstSimplify/shr-nop.ll @@ -244,7 +244,7 @@ define i1 @ashr_ne_opposite_msb(i8 %a) { } ; CHECK-LABEL: @exact_ashr_eq_shift_gt -; CHECK-NEXT : ret i1 false +; CHECK-NEXT: ret i1 false define i1 @exact_ashr_eq_shift_gt(i8 %a) { %shr = ashr exact i8 -2, %a %cmp = icmp eq i8 %shr, -8 @@ -252,7 +252,7 @@ define i1 @exact_ashr_eq_shift_gt(i8 %a) { } ; CHECK-LABEL: @exact_ashr_ne_shift_gt -; CHECK-NEXT : ret i1 true +; CHECK-NEXT: ret i1 true define i1 @exact_ashr_ne_shift_gt(i8 %a) { %shr = ashr exact i8 -2, %a %cmp = icmp ne i8 %shr, -8 @@ -260,7 +260,7 @@ define i1 @exact_ashr_ne_shift_gt(i8 %a) { } ; CHECK-LABEL: @nonexact_ashr_eq_shift_gt -; CHECK-NEXT : ret i1 false +; CHECK-NEXT: ret i1 false define i1 @nonexact_ashr_eq_shift_gt(i8 %a) { %shr = ashr i8 -2, %a %cmp = icmp eq i8 %shr, -8 @@ -268,7 +268,7 @@ define i1 @nonexact_ashr_eq_shift_gt(i8 %a) { } ; CHECK-LABEL: @nonexact_ashr_ne_shift_gt -; CHECK-NEXT : ret i1 true +; CHECK-NEXT: ret i1 true define i1 @nonexact_ashr_ne_shift_gt(i8 %a) { %shr = ashr i8 -2, %a %cmp = icmp ne i8 %shr, -8 @@ -292,7 +292,7 @@ define i1 @exact_lshr_ne_shift_gt(i8 %a) { } ; CHECK-LABEL: @nonexact_lshr_eq_shift_gt -; CHECK-NEXT : ret i1 false +; CHECK-NEXT: ret i1 false define i1 @nonexact_lshr_eq_shift_gt(i8 %a) { %shr = lshr i8 2, %a %cmp = icmp eq i8 %shr, 8 @@ -300,7 +300,7 @@ define i1 @nonexact_lshr_eq_shift_gt(i8 %a) { } ; CHECK-LABEL: @nonexact_lshr_ne_shift_gt -; CHECK-NEXT : ret i1 true +; CHECK-NEXT: ret i1 true define i1 @nonexact_lshr_ne_shift_gt(i8 %a) { %shr = ashr i8 2, %a %cmp = icmp ne i8 %shr, 8 diff --git a/test/Transforms/LICM/pr23608.ll b/test/Transforms/LICM/pr23608.ll index 249bc6bf5f6..fe6fd1a1810 100644 --- a/test/Transforms/LICM/pr23608.ll +++ b/test/Transforms/LICM/pr23608.ll @@ -31,7 +31,7 @@ bb2: ; preds = %while.cond br i1 %tobool, label %bb13, label %bb15 bb13: ; preds = %bb2 -; CHECK-LABEL bb13: +; CHECK-LABEL: bb13: ; CHECK: %tmp8.le = inttoptr %.lcssa7 = phi i32* [ %tmp8, %bb2 ] call void @__msan_warning_noreturn() diff --git a/test/Transforms/RewriteStatepointsForGC/codegen-cond.ll b/test/Transforms/RewriteStatepointsForGC/codegen-cond.ll index 9698537280b..aedce03d255 100644 --- a/test/Transforms/RewriteStatepointsForGC/codegen-cond.ll +++ b/test/Transforms/RewriteStatepointsForGC/codegen-cond.ll @@ -13,7 +13,7 @@ continue: ; CHECK-LABEL: continue: ; CHECK: phi ; CHECK-DAG: [ %p.relocated, %safepoint ] -; CHECK-DAG [ %p, %entry ] +; CHECK-DAG: [ %p, %entry ] ; CHECK: %cond = icmp ; CHECK: br i1 %cond br i1 %cond, label %taken, label %untaken @@ -37,10 +37,10 @@ continue: ; CHECK-LABEL: continue: ; CHECK: phi ; CHECK-DAG: [ %q.relocated, %safepoint ] -; CHECK-DAG [ %q, %entry ] +; CHECK-DAG: [ %q, %entry ] ; CHECK: phi ; CHECK-DAG: [ %p.relocated, %safepoint ] -; CHECK-DAG [ %p, %entry ] +; CHECK-DAG: [ %p, %entry ] ; CHECK: %cond = icmp ; CHECK: br i1 %cond br i1 %cond, label %taken, label %untaken diff --git a/test/Transforms/SROA/basictest.ll b/test/Transforms/SROA/basictest.ll index 25b8e8ba41f..cfd8dd2fb0c 100644 --- a/test/Transforms/SROA/basictest.ll +++ b/test/Transforms/SROA/basictest.ll @@ -1616,7 +1616,7 @@ define i16 @PR24463() { ; a sub-integer that requires extraction *and* extends past the end of the ; alloca. In this case, we should extract the i8 and then zext it to i16. ; -; CHECK-LABEL @PR24463( +; CHECK-LABEL: @PR24463( ; CHECK-NOT: alloca ; CHECK: %[[SHIFT:.*]] = lshr i16 0, 8 ; CHECK: %[[TRUNC:.*]] = trunc i16 %[[SHIFT]] to i8 diff --git a/test/Transforms/StructurizeCFG/nested-loop-order.ll b/test/Transforms/StructurizeCFG/nested-loop-order.ll index fee1ff0433b..8a506c3e396 100644 --- a/test/Transforms/StructurizeCFG/nested-loop-order.ll +++ b/test/Transforms/StructurizeCFG/nested-loop-order.ll @@ -41,7 +41,7 @@ ENDIF: ; preds = %LOOP br i1 %tmp31, label %IF29, label %ENDIF28 ; CHECK: Flow: -; CHECK br i1 %{{[0-9]+}}, label %Flow, label %LOOP +; CHECK: br i1 %{{[0-9]+}}, label %Flow2, label %LOOP ; CHECK: IF29: ; CHECK: br label %Flow1