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[AArch64][PowerPC] add tests for shift sandwich; NFC

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This commit is contained in:
Sanjay Patel 2019-12-12 12:36:10 -05:00
parent 1991907bad
commit f806d650f4
2 changed files with 33 additions and 3 deletions
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13
test/CodeGen/AArch64/shift-amount-mod.ll
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@ -666,3 +666,16 @@ define i64 @reg64_lshr_by_masked_negated_unfolded_add_b(i64 %val, i64 %a, i64 %b
%shifted = lshr i64 %val, %negaaddbitwidthaddb
ret i64 %shifted
}
define i32 @t(i64 %x) {
; CHECK-LABEL: t:
; CHECK: // %bb.0:
; CHECK-NEXT: lsr x8, x0, #13
; CHECK-NEXT: ubfx x0, x8, #4, #28
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
; CHECK-NEXT: ret
%s = lshr i64 %x, 13
%t = trunc i64 %s to i32
%r = lshr i32 %t, 4
ret i32 %r
}

23
test/CodeGen/PowerPC/trunc-srl-load.ll
View File

@ -1,9 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s
; CHECK-LABEL: trunc_srl_load
; CHECK-NOT: lhz 4, 4(0)
; CHECK: lhz 4, 2(0)
define dso_local fastcc void @trunc_srl_load(i32 zeroext %AttrArgNo) {
; CHECK-LABEL: trunc_srl_load:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz 4, 2(0)
; CHECK-NEXT: cmplw 0, 4, 3
; CHECK-NEXT: ble 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %exit
; CHECK-NEXT: .LBB0_2: # %cond.false
entry:
%bf.load.i = load i64, i64* null, align 8
%bf.lshr.i = lshr i64 %bf.load.i, 32
@ -16,3 +21,15 @@ exit: ; preds = %entry
cond.false: ; preds = %entry
unreachable
}
define i32 @sh_trunc_sh(i64 %x) {
; CHECK-LABEL: sh_trunc_sh:
; CHECK: # %bb.0:
; CHECK-NEXT: rldicl 3, 3, 51, 13
; CHECK-NEXT: srwi 3, 3, 4
; CHECK-NEXT: blr
%s = lshr i64 %x, 13
%t = trunc i64 %s to i32
%r = lshr i32 %t, 4
ret i32 %r
}