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Put register classes into namespaces

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llvm-svn: 22925
This commit is contained in:
Chris Lattner 2005-08-19 18:51:57 +00:00
parent 9d61d4a3e4
commit f86654ffde
2 changed files with 9 additions and 8 deletions
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2
lib/Target/SparcV9/SparcV9RegisterInfo.td
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@ -43,7 +43,7 @@ let Namespace = "SparcV9" in {
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7,
def IntRegs : RegisterClass<"V9", i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O6, O7,
L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5, I6, I7]>;

15
lib/Target/X86/X86RegisterInfo.td
View File

@ -72,9 +72,9 @@ let Namespace = "X86" in {
// dependences between upper and lower parts of the register. BL and BH are
// last because they are call clobbered. Both Athlon and P4 chips suffer this
// issue.
def R8 : RegisterClass<i8, 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
def R8 : RegisterClass<"X86", i8, 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
def R16 : RegisterClass<i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
def R16 : RegisterClass<"X86", i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
@ -85,7 +85,7 @@ def R16 : RegisterClass<i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
}];
}
def R32 : RegisterClass<i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
def R32 : RegisterClass<"X86", i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
@ -99,8 +99,8 @@ def R32 : RegisterClass<i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
// FIXME: These registers can contain both integer and fp values. We should
// figure out the right way to deal with that. For now, since they'll be used
// for scalar FP, they are being declared f64
def RXMM : RegisterClass<f64, 32, [XMM0, XMM1, XMM2, XMM3,
XMM4, XMM5, XMM6, XMM7]>;
def RXMM : RegisterClass<"X86", f64, 32,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
// FIXME: This sets up the floating point register files as though they are f64
// values, though they really are f80 values. This will cause us to spill
@ -108,12 +108,13 @@ def RXMM : RegisterClass<f64, 32, [XMM0, XMM1, XMM2, XMM3,
// faster on common hardware. In reality, this should be controlled by a
// command line option or something.
def RFP : RegisterClass<f64, 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
def RFP : RegisterClass<"X86", f64, 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
// Floating point stack registers (these are not allocatable by the
// register allocator - the floating point stackifier is responsible
// for transforming FPn allocations to STn registers)
def RST : RegisterClass<f64, 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
def RST : RegisterClass<"X86", f64, 32,
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const {
return begin();