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[SystemZ] Post-RA scheduler implementation
Post-RA sched strategy and scheduling instruction annotations for z196, zEC12 and z13. This scheduler optimizes decoder grouping and balances processor resources (including side steering the FPd unit instructions). The SystemZHazardRecognizer keeps track of the scheduling state, which can be dumped with -debug-only=misched. Reviers: Ulrich Weigand, Andrew Trick. https://reviews.llvm.org/D17260 llvm-svn: 284704
This commit is contained in:
Jonas Paulsson
parent
64f5482e1d
commit
f8cb784f68
@ -17,12 +17,14 @@ add_llvm_target(SystemZCodeGen
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SystemZConstantPoolValue.cpp
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SystemZElimCompare.cpp
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SystemZFrameLowering.cpp
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SystemZHazardRecognizer.cpp
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SystemZISelDAGToDAG.cpp
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SystemZISelLowering.cpp
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SystemZInstrInfo.cpp
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SystemZLDCleanup.cpp
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SystemZLongBranch.cpp
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SystemZMachineFunctionInfo.cpp
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SystemZMachineScheduler.cpp
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SystemZMCInstLower.cpp
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SystemZRegisterInfo.cpp
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SystemZSelectionDAGInfo.cpp
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@ -13,6 +13,11 @@
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// SystemZ subtargets scheduling models.
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//===----------------------------------------------------------------------===//
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include "SystemZSchedule.td"
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//===----------------------------------------------------------------------===//
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// SystemZ supported processors and features
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//===----------------------------------------------------------------------===//
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337
lib/Target/SystemZ/SystemZHazardRecognizer.cpp
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337
lib/Target/SystemZ/SystemZHazardRecognizer.cpp
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@ -0,0 +1,337 @@
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//=-- SystemZHazardRecognizer.h - SystemZ Hazard Recognizer -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a hazard recognizer for the SystemZ scheduler.
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//
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// This class is used by the SystemZ scheduling strategy to maintain
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// the state during scheduling, and provide cost functions for
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// scheduling candidates. This includes:
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//
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// * Decoder grouping. A decoder group can maximally hold 3 uops, and
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// instructions that always begin a new group should be scheduled when
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// the current decoder group is empty.
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// * Processor resources usage. It is beneficial to balance the use of
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// resources.
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//
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// ===---------------------------------------------------------------------===//
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#include "SystemZHazardRecognizer.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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#define DEBUG_TYPE "misched"
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// This is the limit of processor resource usage at which the
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// scheduler should try to look for other instructions (not using the
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// critical resource).
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cl::opt<int> ProcResCostLim("procres-cost-lim", cl::Hidden,
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cl::desc("The OOO window for processor "
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"resources during scheduling."),
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cl::init(8));
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SystemZHazardRecognizer::
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SystemZHazardRecognizer(const MachineSchedContext *C) : DAG(nullptr),
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SchedModel(nullptr) {}
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unsigned SystemZHazardRecognizer::
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getNumDecoderSlots(SUnit *SU) const {
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const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
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if (!SC->isValid())
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return 0; // IMPLICIT_DEF / KILL -- will not make impact in output.
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if (SC->BeginGroup) {
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if (!SC->EndGroup)
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return 2; // Cracked instruction
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else
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return 3; // Expanded/group-alone instruction
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}
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return 1; // Normal instruction
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}
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unsigned SystemZHazardRecognizer::getCurrCycleIdx() {
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unsigned Idx = CurrGroupSize;
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if (GrpCount % 2)
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Idx += 3;
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return Idx;
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}
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ScheduleHazardRecognizer::HazardType SystemZHazardRecognizer::
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getHazardType(SUnit *m, int Stalls) {
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return (fitsIntoCurrentGroup(m) ? NoHazard : Hazard);
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}
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void SystemZHazardRecognizer::Reset() {
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CurrGroupSize = 0;
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clearProcResCounters();
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GrpCount = 0;
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LastFPdOpCycleIdx = UINT_MAX;
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DEBUG(CurGroupDbg = "";);
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}
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bool
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SystemZHazardRecognizer::fitsIntoCurrentGroup(SUnit *SU) const {
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const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
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if (!SC->isValid())
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return true;
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// A cracked instruction only fits into schedule if the current
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// group is empty.
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if (SC->BeginGroup)
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return (CurrGroupSize == 0);
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// Since a full group is handled immediately in EmitInstruction(),
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// SU should fit into current group. NumSlots should be 1 or 0,
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// since it is not a cracked or expanded instruction.
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assert ((getNumDecoderSlots(SU) <= 1) && (CurrGroupSize < 3) &&
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"Expected normal instruction to fit in non-full group!");
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return true;
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}
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void SystemZHazardRecognizer::nextGroup(bool DbgOutput) {
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if (CurrGroupSize > 0) {
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DEBUG(dumpCurrGroup("Completed decode group"));
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DEBUG(CurGroupDbg = "";);
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GrpCount++;
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// Reset counter for next group.
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CurrGroupSize = 0;
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// Decrease counters for execution units by one.
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for (unsigned i = 0; i < SchedModel->getNumProcResourceKinds(); ++i)
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if (ProcResourceCounters[i] > 0)
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ProcResourceCounters[i]--;
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// Clear CriticalResourceIdx if it is now below the threshold.
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if (CriticalResourceIdx != UINT_MAX &&
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(ProcResourceCounters[CriticalResourceIdx] <=
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ProcResCostLim))
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CriticalResourceIdx = UINT_MAX;
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}
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DEBUG(if (DbgOutput)
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dumpProcResourceCounters(););
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}
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#ifndef NDEBUG // Debug output
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void SystemZHazardRecognizer::dumpSU(SUnit *SU, raw_ostream &OS) const {
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OS << "SU(" << SU->NodeNum << "):";
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OS << SchedModel->getInstrInfo()->getName(SU->getInstr()->getOpcode());
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const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
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if (!SC->isValid())
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return;
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for (TargetSchedModel::ProcResIter
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PI = SchedModel->getWriteProcResBegin(SC),
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PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
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const MCProcResourceDesc &PRD =
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*SchedModel->getProcResource(PI->ProcResourceIdx);
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std::string FU(PRD.Name);
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// trim e.g. Z13_FXaUnit -> FXa
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FU = FU.substr(FU.find("_") + 1);
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FU.resize(FU.find("Unit"));
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OS << "/" << FU;
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if (PI->Cycles > 1)
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OS << "(" << PI->Cycles << "cyc)";
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}
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if (SC->NumMicroOps > 1)
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OS << "/" << SC->NumMicroOps << "uops";
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if (SC->BeginGroup && SC->EndGroup)
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OS << "/GroupsAlone";
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else if (SC->BeginGroup)
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OS << "/BeginsGroup";
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else if (SC->EndGroup)
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OS << "/EndsGroup";
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if (SU->isUnbuffered)
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OS << "/Unbuffered";
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}
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void SystemZHazardRecognizer::dumpCurrGroup(std::string Msg) const {
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dbgs() << "+++ " << Msg;
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dbgs() << ": ";
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if (CurGroupDbg.empty())
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dbgs() << " <empty>\n";
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else {
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dbgs() << "{ " << CurGroupDbg << " }";
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dbgs() << " (" << CurrGroupSize << " decoder slot"
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<< (CurrGroupSize > 1 ? "s":"")
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<< ")\n";
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}
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}
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void SystemZHazardRecognizer::dumpProcResourceCounters() const {
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bool any = false;
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for (unsigned i = 0; i < SchedModel->getNumProcResourceKinds(); ++i)
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if (ProcResourceCounters[i] > 0) {
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any = true;
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break;
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}
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if (!any)
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return;
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dbgs() << "+++ Resource counters:\n";
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for (unsigned i = 0; i < SchedModel->getNumProcResourceKinds(); ++i)
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if (ProcResourceCounters[i] > 0) {
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dbgs() << "+++ Extra schedule for execution unit "
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<< SchedModel->getProcResource(i)->Name
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<< ": " << ProcResourceCounters[i] << "\n";
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any = true;
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}
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}
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#endif //NDEBUG
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void SystemZHazardRecognizer::clearProcResCounters() {
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ProcResourceCounters.assign(SchedModel->getNumProcResourceKinds(), 0);
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CriticalResourceIdx = UINT_MAX;
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}
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// Update state with SU as the next scheduled unit.
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void SystemZHazardRecognizer::
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EmitInstruction(SUnit *SU) {
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const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
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DEBUG( dumpCurrGroup("Decode group before emission"););
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// If scheduling an SU that must begin a new decoder group, move on
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// to next group.
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if (!fitsIntoCurrentGroup(SU))
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nextGroup();
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DEBUG( dbgs() << "+++ HazardRecognizer emitting "; dumpSU(SU, dbgs());
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dbgs() << "\n";
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raw_string_ostream cgd(CurGroupDbg);
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if (CurGroupDbg.length())
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cgd << ", ";
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dumpSU(SU, cgd););
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// After returning from a call, we don't know much about the state.
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if (SU->getInstr()->isCall()) {
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DEBUG (dbgs() << "+++ Clearing state after call.\n";);
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clearProcResCounters();
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LastFPdOpCycleIdx = UINT_MAX;
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CurrGroupSize += getNumDecoderSlots(SU);
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assert (CurrGroupSize <= 3);
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nextGroup();
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return;
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}
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// Increase counter for execution unit(s).
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for (TargetSchedModel::ProcResIter
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PI = SchedModel->getWriteProcResBegin(SC),
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PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
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// Don't handle FPd together with the other resources.
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if (SchedModel->getProcResource(PI->ProcResourceIdx)->BufferSize == 1)
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continue;
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int &CurrCounter =
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ProcResourceCounters[PI->ProcResourceIdx];
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CurrCounter += PI->Cycles;
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// Check if this is now the new critical resource.
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if ((CurrCounter > ProcResCostLim) &&
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(CriticalResourceIdx == UINT_MAX ||
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(PI->ProcResourceIdx != CriticalResourceIdx &&
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CurrCounter >
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ProcResourceCounters[CriticalResourceIdx]))) {
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DEBUG( dbgs() << "+++ New critical resource: "
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<< SchedModel->getProcResource(PI->ProcResourceIdx)->Name
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<< "\n";);
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CriticalResourceIdx = PI->ProcResourceIdx;
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}
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}
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// Make note of an instruction that uses a blocking resource (FPd).
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if (SU->isUnbuffered) {
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LastFPdOpCycleIdx = getCurrCycleIdx();
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DEBUG (dbgs() << "+++ Last FPd cycle index: "
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<< LastFPdOpCycleIdx << "\n";);
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}
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// Insert SU into current group by increasing number of slots used
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// in current group.
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CurrGroupSize += getNumDecoderSlots(SU);
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assert (CurrGroupSize <= 3);
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// Check if current group is now full/ended. If so, move on to next
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// group to be ready to evaluate more candidates.
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if (CurrGroupSize == 3 || SC->EndGroup)
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nextGroup();
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}
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int SystemZHazardRecognizer::groupingCost(SUnit *SU) const {
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const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
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if (!SC->isValid())
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return 0;
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// If SU begins new group, it can either break a current group early
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// or fit naturally if current group is empty (negative cost).
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if (SC->BeginGroup) {
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if (CurrGroupSize)
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return 3 - CurrGroupSize;
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return -1;
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}
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// Similarly, a group-ending SU may either fit well (last in group), or
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// end the group prematurely.
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if (SC->EndGroup) {
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unsigned resultingGroupSize =
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(CurrGroupSize + getNumDecoderSlots(SU));
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if (resultingGroupSize < 3)
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return (3 - resultingGroupSize);
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return -1;
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}
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// Most instructions can be placed in any decoder slot.
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return 0;
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}
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bool SystemZHazardRecognizer::isFPdOpPreferred_distance(const SUnit *SU) {
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assert (SU->isUnbuffered);
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// If this is the first FPd op, it should be scheduled high.
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if (LastFPdOpCycleIdx == UINT_MAX)
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return true;
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// If this is not the first PFd op, it should go into the other side
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// of the processor to use the other FPd unit there. This should
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// generally happen if two FPd ops are placed with 2 other
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// instructions between them (modulo 6).
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if (LastFPdOpCycleIdx > getCurrCycleIdx())
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return ((LastFPdOpCycleIdx - getCurrCycleIdx()) == 3);
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return ((getCurrCycleIdx() - LastFPdOpCycleIdx) == 3);
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}
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int SystemZHazardRecognizer::
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resourcesCost(SUnit *SU) {
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int Cost = 0;
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const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
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if (!SC->isValid())
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return 0;
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// For a FPd op, either return min or max value as indicated by the
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// distance to any prior FPd op.
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if (SU->isUnbuffered)
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Cost = (isFPdOpPreferred_distance(SU) ? INT_MIN : INT_MAX);
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// For other instructions, give a cost to the use of the critical resource.
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else if (CriticalResourceIdx != UINT_MAX) {
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for (TargetSchedModel::ProcResIter
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PI = SchedModel->getWriteProcResBegin(SC),
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PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI)
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if (PI->ProcResourceIdx == CriticalResourceIdx)
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Cost = PI->Cycles;
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}
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return Cost;
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}
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128
lib/Target/SystemZ/SystemZHazardRecognizer.h
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128
lib/Target/SystemZ/SystemZHazardRecognizer.h
Normal file
@ -0,0 +1,128 @@
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//=-- SystemZHazardRecognizer.h - SystemZ Hazard Recognizer -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares a hazard recognizer for the SystemZ scheduler.
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//
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// This class is used by the SystemZ scheduling strategy to maintain
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// the state during scheduling, and provide cost functions for
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// scheduling candidates. This includes:
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//
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// * Decoder grouping. A decoder group can maximally hold 3 uops, and
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// instructions that always begin a new group should be scheduled when
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// the current decoder group is empty.
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// * Processor resources usage. It is beneficial to balance the use of
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// resources.
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//
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// ===---------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZHAZARDRECOGNIZER_H
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#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZHAZARDRECOGNIZER_H
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#include "SystemZSubtarget.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/raw_ostream.h"
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#include <string>
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namespace llvm {
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/// SystemZHazardRecognizer maintains the state during scheduling.
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class SystemZHazardRecognizer : public ScheduleHazardRecognizer {
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ScheduleDAGMI *DAG;
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const TargetSchedModel *SchedModel;
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/// Keep track of the number of decoder slots used in the current
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/// decoder group.
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unsigned CurrGroupSize;
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/// The tracking of resources here are quite similar to the common
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/// code use of a critical resource. However, z13 differs in the way
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/// that it has two processor sides which may be interesting to
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/// model in the future (a work in progress).
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/// Counters for the number of uops scheduled per processor
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/// resource.
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SmallVector<int, 0> ProcResourceCounters;
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/// This is the resource with the greatest queue, which the
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/// scheduler tries to avoid.
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unsigned CriticalResourceIdx;
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/// Return the number of decoder slots MI requires.
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inline unsigned getNumDecoderSlots(SUnit *SU) const;
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/// Return true if MI fits into current decoder group.
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bool fitsIntoCurrentGroup(SUnit *SU) const;
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/// Two decoder groups per cycle are formed (for z13), meaning 2x3
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/// instructions. This function returns a number between 0 and 5,
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/// representing the current decoder slot of the current cycle.
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unsigned getCurrCycleIdx();
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/// LastFPdOpCycleIdx stores the numbeer returned by getCurrCycleIdx()
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/// when a stalling operation is scheduled (which uses the FPd resource).
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unsigned LastFPdOpCycleIdx;
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/// A counter of decoder groups scheduled.
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unsigned GrpCount;
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unsigned getCurrGroupSize() {return CurrGroupSize;};
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/// Start next decoder group.
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void nextGroup(bool DbgOutput = true);
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/// Clear all counters for processor resources.
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void clearProcResCounters();
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/// With the goal of alternating processor sides for stalling (FPd)
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/// ops, return true if it seems good to schedule an FPd op next.
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bool isFPdOpPreferred_distance(const SUnit *SU);
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public:
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SystemZHazardRecognizer(const MachineSchedContext *C);
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void setDAG(ScheduleDAGMI *dag) {
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DAG = dag;
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SchedModel = dag->getSchedModel();
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}
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HazardType getHazardType(SUnit *m, int Stalls = 0) override;
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void Reset() override;
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void EmitInstruction(SUnit *SU) override;
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// Cost functions used by SystemZPostRASchedStrategy while
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// evaluating candidates.
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|
||||
/// Return the cost of decoder grouping for SU. If SU must start a
|
||||
/// new decoder group, this is negative if this fits the schedule or
|
||||
/// positive if it would mean ending a group prematurely. For normal
|
||||
/// instructions this returns 0.
|
||||
int groupingCost(SUnit *SU) const;
|
||||
|
||||
/// Return the cost of SU in regards to processor resources usage.
|
||||
/// A positive value means it would be better to wait with SU, while
|
||||
/// a negative value means it would be good to schedule SU next.
|
||||
int resourcesCost(SUnit *SU);
|
||||
|
||||
#ifndef NDEBUG
|
||||
// Debug dumping.
|
||||
std::string CurGroupDbg; // current group as text
|
||||
void dumpSU(SUnit *SU, raw_ostream &OS) const;
|
||||
void dumpCurrGroup(std::string Msg = "") const;
|
||||
void dumpProcResourceCounters() const;
|
||||
#endif
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
|
||||
#endif /* LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZHAZARDRECOGNIZER_H */
|
||||
@ -2996,6 +2996,7 @@ class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let usesCustomInserter = 1;
|
||||
let hasNoSchedulingInfo = 1;
|
||||
}
|
||||
|
||||
// Specializations of AtomicLoadWBinary.
|
||||
@ -3022,6 +3023,7 @@ class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let usesCustomInserter = 1;
|
||||
let hasNoSchedulingInfo = 1;
|
||||
}
|
||||
|
||||
// Specializations of AtomicLoadWBinary.
|
||||
@ -3040,7 +3042,7 @@ multiclass MemorySS<string mnemonic, bits<8> opcode,
|
||||
def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
|
||||
bdaddr12only:$BD2),
|
||||
mnemonic##"\t$BDL1, $BD2", []>;
|
||||
let usesCustomInserter = 1 in {
|
||||
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
|
||||
def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
|
||||
imm64:$length),
|
||||
[(sequence bdaddr12only:$dest, bdaddr12only:$src,
|
||||
@ -3066,7 +3068,7 @@ multiclass StringRRE<string mnemonic, bits<16> opcode,
|
||||
let Constraints = "$R1 = $R1src, $R2 = $R2src";
|
||||
let DisableEncoding = "$R1src, $R2src";
|
||||
}
|
||||
let usesCustomInserter = 1 in
|
||||
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
|
||||
def Loop : Pseudo<(outs GR64:$end),
|
||||
(ins GR64:$start1, GR64:$start2, GR32:$char),
|
||||
[(set GR64:$end, (operator GR64:$start1, GR64:$start2,
|
||||
|
||||
@ -1516,3 +1516,38 @@ void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
|
||||
}
|
||||
BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
|
||||
}
|
||||
|
||||
bool SystemZInstrInfo::
|
||||
areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
|
||||
AliasAnalysis *AA) const {
|
||||
|
||||
if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
|
||||
return false;
|
||||
|
||||
// If mem-operands show that the same address Value is used by both
|
||||
// instructions, check for non-overlapping offsets and widths. Not
|
||||
// sure if a register based analysis would be an improvement...
|
||||
|
||||
MachineMemOperand *MMOa = *MIa.memoperands_begin();
|
||||
MachineMemOperand *MMOb = *MIb.memoperands_begin();
|
||||
const Value *VALa = MMOa->getValue();
|
||||
const Value *VALb = MMOb->getValue();
|
||||
bool SameVal = (VALa && VALb && (VALa == VALb));
|
||||
if (!SameVal) {
|
||||
const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
|
||||
const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
|
||||
if (PSVa && PSVb && (PSVa == PSVb))
|
||||
SameVal = true;
|
||||
}
|
||||
if (SameVal) {
|
||||
int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
|
||||
int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
|
||||
int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
|
||||
int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
|
||||
int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
|
||||
if (LowOffset + LowWidth <= HighOffset)
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -263,6 +263,14 @@ public:
|
||||
void loadImmediate(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned Reg, uint64_t Value) const;
|
||||
|
||||
// Sometimes, it is possible for the target to tell, even without
|
||||
// aliasing information, that two MIs access different memory
|
||||
// addresses. This function returns true if two MIs access different
|
||||
// memory addresses and false otherwise.
|
||||
bool
|
||||
areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
|
||||
AliasAnalysis *AA = nullptr) const override;
|
||||
};
|
||||
} // end namespace llvm
|
||||
|
||||
|
||||
@ -11,10 +11,12 @@
|
||||
// Stack allocation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
|
||||
[(callseq_start timm:$amt)]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
|
||||
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
let hasNoSchedulingInfo = 1 in {
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
|
||||
[(callseq_start timm:$amt)]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
|
||||
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
}
|
||||
|
||||
let hasSideEffects = 0 in {
|
||||
// Takes as input the value of the stack pointer after a dynamic allocation
|
||||
@ -1410,7 +1412,7 @@ let hasSideEffects = 1 in
|
||||
def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
|
||||
|
||||
// A pseudo instruction that serves as a compiler barrier.
|
||||
let hasSideEffects = 1 in
|
||||
let hasSideEffects = 1, hasNoSchedulingInfo = 1 in
|
||||
def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>;
|
||||
|
||||
let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
|
||||
@ -1546,6 +1548,7 @@ def ATOMIC_CMP_SWAPW
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
let usesCustomInserter = 1;
|
||||
let hasNoSchedulingInfo = 1;
|
||||
}
|
||||
|
||||
let Defs = [CC] in {
|
||||
|
||||
@ -414,7 +414,7 @@ let Predicates = [FeatureVector] in {
|
||||
def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>;
|
||||
|
||||
// Count trailing zeros.
|
||||
def VCLT : UnaryVRRaGeneric<"vctz", 0xE752>;
|
||||
def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>;
|
||||
def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>;
|
||||
def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>;
|
||||
def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>;
|
||||
|
||||
153
lib/Target/SystemZ/SystemZMachineScheduler.cpp
Normal file
153
lib/Target/SystemZ/SystemZMachineScheduler.cpp
Normal file
@ -0,0 +1,153 @@
|
||||
//-- SystemZMachineScheduler.cpp - SystemZ Scheduler Interface -*- C++ -*---==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// -------------------------- Post RA scheduling ---------------------------- //
|
||||
// SystemZPostRASchedStrategy is a scheduling strategy which is plugged into
|
||||
// the MachineScheduler. It has a sorted Available set of SUs and a pickNode()
|
||||
// implementation that looks to optimize decoder grouping and balance the
|
||||
// usage of processor resources.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "SystemZMachineScheduler.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "misched"
|
||||
|
||||
#ifndef NDEBUG
|
||||
// Print the set of SUs
|
||||
void SystemZPostRASchedStrategy::SUSet::
|
||||
dump(SystemZHazardRecognizer &HazardRec) {
|
||||
dbgs() << "{";
|
||||
for (auto &SU : *this) {
|
||||
HazardRec.dumpSU(SU, dbgs());
|
||||
if (SU != *rbegin())
|
||||
dbgs() << ", ";
|
||||
}
|
||||
dbgs() << "}\n";
|
||||
}
|
||||
#endif
|
||||
|
||||
SystemZPostRASchedStrategy::
|
||||
SystemZPostRASchedStrategy(const MachineSchedContext *C)
|
||||
: DAG(nullptr), HazardRec(C) {}
|
||||
|
||||
void SystemZPostRASchedStrategy::initialize(ScheduleDAGMI *dag) {
|
||||
DAG = dag;
|
||||
HazardRec.setDAG(dag);
|
||||
HazardRec.Reset();
|
||||
}
|
||||
|
||||
// Pick the next node to schedule.
|
||||
SUnit *SystemZPostRASchedStrategy::pickNode(bool &IsTopNode) {
|
||||
// Only scheduling top-down.
|
||||
IsTopNode = true;
|
||||
|
||||
if (Available.empty())
|
||||
return nullptr;
|
||||
|
||||
// If only one choice, return it.
|
||||
if (Available.size() == 1) {
|
||||
DEBUG (dbgs() << "+++ Only one: ";
|
||||
HazardRec.dumpSU(*Available.begin(), dbgs()); dbgs() << "\n";);
|
||||
return *Available.begin();
|
||||
}
|
||||
|
||||
// All nodes that are possible to schedule are stored by in the
|
||||
// Available set.
|
||||
DEBUG(dbgs() << "+++ Available: "; Available.dump(HazardRec););
|
||||
|
||||
Candidate Best;
|
||||
for (auto *SU : Available) {
|
||||
|
||||
// SU is the next candidate to be compared against current Best.
|
||||
Candidate c(SU, HazardRec);
|
||||
|
||||
// Remeber which SU is the best candidate.
|
||||
if (Best.SU == nullptr || c < Best) {
|
||||
Best = c;
|
||||
DEBUG(dbgs() << "+++ Best sofar: ";
|
||||
HazardRec.dumpSU(Best.SU, dbgs());
|
||||
if (Best.GroupingCost != 0)
|
||||
dbgs() << "\tGrouping cost:" << Best.GroupingCost;
|
||||
if (Best.ResourcesCost != 0)
|
||||
dbgs() << " Resource cost:" << Best.ResourcesCost;
|
||||
dbgs() << " Height:" << Best.SU->getHeight();
|
||||
dbgs() << "\n";);
|
||||
}
|
||||
|
||||
// Once we know we have seen all SUs that affect grouping or use unbuffered
|
||||
// resources, we can stop iterating if Best looks good.
|
||||
if (!SU->isScheduleHigh && Best.noCost())
|
||||
break;
|
||||
}
|
||||
|
||||
assert (Best.SU != nullptr);
|
||||
return Best.SU;
|
||||
}
|
||||
|
||||
SystemZPostRASchedStrategy::Candidate::
|
||||
Candidate(SUnit *SU_, SystemZHazardRecognizer &HazardRec) : Candidate() {
|
||||
SU = SU_;
|
||||
|
||||
// Check the grouping cost. For a node that must begin / end a
|
||||
// group, it is positive if it would do so prematurely, or negative
|
||||
// if it would fit naturally into the schedule.
|
||||
GroupingCost = HazardRec.groupingCost(SU);
|
||||
|
||||
// Check the resources cost for this SU.
|
||||
ResourcesCost = HazardRec.resourcesCost(SU);
|
||||
}
|
||||
|
||||
bool SystemZPostRASchedStrategy::Candidate::
|
||||
operator<(const Candidate &other) {
|
||||
|
||||
// Check decoder grouping.
|
||||
if (GroupingCost < other.GroupingCost)
|
||||
return true;
|
||||
if (GroupingCost > other.GroupingCost)
|
||||
return false;
|
||||
|
||||
// Compare the use of resources.
|
||||
if (ResourcesCost < other.ResourcesCost)
|
||||
return true;
|
||||
if (ResourcesCost > other.ResourcesCost)
|
||||
return false;
|
||||
|
||||
// Higher SU is otherwise generally better.
|
||||
if (SU->getHeight() > other.SU->getHeight())
|
||||
return true;
|
||||
if (SU->getHeight() < other.SU->getHeight())
|
||||
return false;
|
||||
|
||||
// If all same, fall back to original order.
|
||||
if (SU->NodeNum < other.SU->NodeNum)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void SystemZPostRASchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
|
||||
DEBUG(dbgs() << "+++ Scheduling SU(" << SU->NodeNum << ")\n";);
|
||||
|
||||
// Remove SU from Available set and update HazardRec.
|
||||
Available.erase(SU);
|
||||
HazardRec.EmitInstruction(SU);
|
||||
}
|
||||
|
||||
void SystemZPostRASchedStrategy::releaseTopNode(SUnit *SU) {
|
||||
// Set isScheduleHigh flag on all SUs that we want to consider first in
|
||||
// pickNode().
|
||||
const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
|
||||
bool AffectsGrouping = (SC->isValid() && (SC->BeginGroup || SC->EndGroup));
|
||||
SU->isScheduleHigh = (AffectsGrouping || SU->isUnbuffered);
|
||||
|
||||
// Put all released SUs in the Available set.
|
||||
Available.insert(SU);
|
||||
}
|
||||
112
lib/Target/SystemZ/SystemZMachineScheduler.h
Normal file
112
lib/Target/SystemZ/SystemZMachineScheduler.h
Normal file
@ -0,0 +1,112 @@
|
||||
//==-- SystemZMachineScheduler.h - SystemZ Scheduler Interface -*- C++ -*---==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// -------------------------- Post RA scheduling ---------------------------- //
|
||||
// SystemZPostRASchedStrategy is a scheduling strategy which is plugged into
|
||||
// the MachineScheduler. It has a sorted Available set of SUs and a pickNode()
|
||||
// implementation that looks to optimize decoder grouping and balance the
|
||||
// usage of processor resources.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "SystemZInstrInfo.h"
|
||||
#include "SystemZHazardRecognizer.h"
|
||||
#include "llvm/CodeGen/MachineScheduler.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
|
||||
#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H
|
||||
#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
namespace llvm {
|
||||
|
||||
/// A MachineSchedStrategy implementation for SystemZ post RA scheduling.
|
||||
class SystemZPostRASchedStrategy : public MachineSchedStrategy {
|
||||
ScheduleDAGMI *DAG;
|
||||
|
||||
/// A candidate during instruction evaluation.
|
||||
struct Candidate {
|
||||
SUnit *SU;
|
||||
|
||||
/// The decoding cost.
|
||||
int GroupingCost;
|
||||
|
||||
/// The processor resources cost.
|
||||
int ResourcesCost;
|
||||
|
||||
Candidate() : SU(nullptr), GroupingCost(0), ResourcesCost(0) {}
|
||||
Candidate(SUnit *SU_, SystemZHazardRecognizer &HazardRec);
|
||||
|
||||
// Compare two candidates.
|
||||
bool operator<(const Candidate &other);
|
||||
|
||||
// Check if this node is free of cost ("as good as any").
|
||||
bool inline noCost() {
|
||||
return (GroupingCost <= 0 && !ResourcesCost);
|
||||
}
|
||||
};
|
||||
|
||||
// A sorter for the Available set that makes sure that SUs are considered
|
||||
// in the best order.
|
||||
struct SUSorter {
|
||||
bool operator() (SUnit *lhs, SUnit *rhs) const {
|
||||
if (lhs->isScheduleHigh && !rhs->isScheduleHigh)
|
||||
return true;
|
||||
if (!lhs->isScheduleHigh && rhs->isScheduleHigh)
|
||||
return false;
|
||||
|
||||
if (lhs->getHeight() > rhs->getHeight())
|
||||
return true;
|
||||
else if (lhs->getHeight() < rhs->getHeight())
|
||||
return false;
|
||||
|
||||
return (lhs->NodeNum < rhs->NodeNum);
|
||||
}
|
||||
};
|
||||
// A set of SUs with a sorter and dump method.
|
||||
struct SUSet : std::set<SUnit*, SUSorter> {
|
||||
#ifndef NDEBUG
|
||||
void dump(SystemZHazardRecognizer &HazardRec);
|
||||
#endif
|
||||
};
|
||||
|
||||
/// The set of available SUs to schedule next.
|
||||
SUSet Available;
|
||||
|
||||
// HazardRecognizer that tracks the scheduler state for the current
|
||||
// region.
|
||||
SystemZHazardRecognizer HazardRec;
|
||||
|
||||
public:
|
||||
SystemZPostRASchedStrategy(const MachineSchedContext *C);
|
||||
|
||||
/// PostRA scheduling does not track pressure.
|
||||
bool shouldTrackPressure() const override { return false; }
|
||||
|
||||
/// Initialize the strategy after building the DAG for a new region.
|
||||
void initialize(ScheduleDAGMI *dag) override;
|
||||
|
||||
/// Pick the next node to schedule, or return NULL.
|
||||
SUnit *pickNode(bool &IsTopNode) override;
|
||||
|
||||
/// ScheduleDAGMI has scheduled an instruction - tell HazardRec
|
||||
/// about it.
|
||||
void schedNode(SUnit *SU, bool IsTopNode) override;
|
||||
|
||||
/// SU has had all predecessor dependencies resolved. Put it into
|
||||
/// Available.
|
||||
void releaseTopNode(SUnit *SU) override;
|
||||
|
||||
/// Currently only scheduling top-down, so this method is empty.
|
||||
void releaseBottomNode(SUnit *SU) override {};
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
|
||||
#endif /* LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H */
|
||||
@ -83,17 +83,18 @@ def FeatureNoVector : SystemZMissingFeature<"Vector">;
|
||||
|
||||
def : Processor<"generic", NoItineraries, []>;
|
||||
def : Processor<"z10", NoItineraries, []>;
|
||||
def : Processor<"z196", NoItineraries,
|
||||
def : ProcessorModel<"z196", Z196Model,
|
||||
[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
|
||||
FeatureFPExtension, FeaturePopulationCount,
|
||||
FeatureFastSerialization, FeatureInterlockedAccess1]>;
|
||||
def : Processor<"zEC12", NoItineraries,
|
||||
def : ProcessorModel<"zEC12", ZEC12Model,
|
||||
[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
|
||||
FeatureFPExtension, FeaturePopulationCount,
|
||||
FeatureFastSerialization, FeatureInterlockedAccess1,
|
||||
FeatureMiscellaneousExtensions,
|
||||
FeatureTransactionalExecution, FeatureProcessorAssist]>;
|
||||
def : Processor<"z13", NoItineraries,
|
||||
|
||||
def : ProcessorModel<"z13", Z13Model,
|
||||
[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
|
||||
FeatureFPExtension, FeaturePopulationCount,
|
||||
FeatureFastSerialization, FeatureInterlockedAccess1,
|
||||
|
||||
70
lib/Target/SystemZ/SystemZSchedule.td
Normal file
70
lib/Target/SystemZ/SystemZSchedule.td
Normal file
@ -0,0 +1,70 @@
|
||||
//==-- SystemZSchedule.td - SystemZ Scheduling Definitions ----*- tblgen -*-==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Scheduler resources
|
||||
|
||||
// These three resources are used to express decoder grouping rules.
|
||||
// The number of decoder slots needed by an instructions is normally
|
||||
// one. For a cracked instruction (BeginGroup && !EndGroup) it is
|
||||
// two. Expanded instructions (BeginGroup && EndGroup) group alone.
|
||||
def GroupAlone : SchedWrite;
|
||||
def BeginGroup : SchedWrite;
|
||||
def EndGroup : SchedWrite;
|
||||
|
||||
// Latencies, to make code a bit neater. If more than one resource is
|
||||
// used for an instruction, the greatest latency (not the sum) will be
|
||||
// output by Tablegen. Therefore, in such cases one of these resources
|
||||
// is needed.
|
||||
def Lat2 : SchedWrite;
|
||||
def Lat3 : SchedWrite;
|
||||
def Lat4 : SchedWrite;
|
||||
def Lat5 : SchedWrite;
|
||||
def Lat6 : SchedWrite;
|
||||
def Lat7 : SchedWrite;
|
||||
def Lat8 : SchedWrite;
|
||||
def Lat9 : SchedWrite;
|
||||
def Lat10 : SchedWrite;
|
||||
def Lat11 : SchedWrite;
|
||||
def Lat12 : SchedWrite;
|
||||
def Lat15 : SchedWrite;
|
||||
def Lat20 : SchedWrite;
|
||||
def Lat30 : SchedWrite;
|
||||
|
||||
// Fixed-point
|
||||
def FXa : SchedWrite;
|
||||
def FXb : SchedWrite;
|
||||
def FXU : SchedWrite;
|
||||
|
||||
// Load/store unit
|
||||
def LSU : SchedWrite;
|
||||
|
||||
// Model a return without latency, otherwise if-converter will model
|
||||
// extra cost and abort (currently there is an assert that checks that
|
||||
// all instructions have at least one uop).
|
||||
def LSU_lat1 : SchedWrite;
|
||||
|
||||
// Floating point unit (zEC12 and earlier)
|
||||
def FPU : SchedWrite;
|
||||
|
||||
// Vector sub units (z13)
|
||||
def VecBF : SchedWrite;
|
||||
def VecDF : SchedWrite;
|
||||
def VecFPd : SchedWrite; // Blocking BFP div/sqrt unit.
|
||||
def VecMul : SchedWrite;
|
||||
def VecStr : SchedWrite;
|
||||
def VecXsPm : SchedWrite;
|
||||
|
||||
// Virtual branching unit
|
||||
def VBU : SchedWrite;
|
||||
|
||||
|
||||
include "SystemZScheduleZ13.td"
|
||||
include "SystemZScheduleZEC12.td"
|
||||
include "SystemZScheduleZ196.td"
|
||||
|
||||
991
lib/Target/SystemZ/SystemZScheduleZ13.td
Normal file
991
lib/Target/SystemZ/SystemZScheduleZ13.td
Normal file
@ -0,0 +1,991 @@
|
||||
//-- SystemZScheduleZ13.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines the machine model for Z13 to support instruction
|
||||
// scheduling and other instruction cost heuristics.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def Z13Model : SchedMachineModel {
|
||||
|
||||
let IssueWidth = 6; // 2 * 3 instructions decoded per cycle.
|
||||
let MicroOpBufferSize = 60; // Issue queues
|
||||
let LoadLatency = 1; // Optimistic load latency.
|
||||
|
||||
let PostRAScheduler = 1;
|
||||
|
||||
// Extra cycles for a mispredicted branch.
|
||||
let MispredictPenalty = 8;
|
||||
}
|
||||
|
||||
let SchedModel = Z13Model in {
|
||||
|
||||
// These definitions could be put in a subtarget common include file,
|
||||
// but it seems the include system in Tablegen currently rejects
|
||||
// multiple includes of same file.
|
||||
def : WriteRes<GroupAlone, []> {
|
||||
let NumMicroOps = 0;
|
||||
let BeginGroup = 1;
|
||||
let EndGroup = 1;
|
||||
}
|
||||
def : WriteRes<BeginGroup, []> {
|
||||
let NumMicroOps = 0;
|
||||
let BeginGroup = 1;
|
||||
}
|
||||
def : WriteRes<EndGroup, []> {
|
||||
let NumMicroOps = 0;
|
||||
let EndGroup = 1;
|
||||
}
|
||||
def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
|
||||
|
||||
// Execution units.
|
||||
def Z13_FXaUnit : ProcResource<2>;
|
||||
def Z13_FXbUnit : ProcResource<2>;
|
||||
def Z13_LSUnit : ProcResource<2>;
|
||||
def Z13_VecBFUnit : ProcResource<2>;
|
||||
def Z13_VecDFUnit : ProcResource<2>;
|
||||
def Z13_VecFPdUnit : ProcResource<2> { let BufferSize = 1; /* blocking */ }
|
||||
def Z13_VecMulUnit : ProcResource<2>;
|
||||
def Z13_VecStrUnit : ProcResource<2>;
|
||||
def Z13_VecXsPmUnit : ProcResource<2>;
|
||||
def Z13_VBUnit : ProcResource<1>;
|
||||
|
||||
// Subtarget specific definitions of scheduling resources.
|
||||
def : WriteRes<FXa, [Z13_FXaUnit]> { let Latency = 1; }
|
||||
def : WriteRes<FXb, [Z13_FXbUnit]> { let Latency = 1; }
|
||||
def : WriteRes<LSU, [Z13_LSUnit]> { let Latency = 4; }
|
||||
def : WriteRes<VecBF, [Z13_VecBFUnit]> { let Latency = 8; }
|
||||
def : WriteRes<VecDF, [Z13_VecDFUnit]>;
|
||||
def : WriteRes<VecFPd, [Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
|
||||
Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
|
||||
Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
|
||||
Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
|
||||
Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
|
||||
Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
|
||||
Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
|
||||
Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
|
||||
Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
|
||||
Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit]>
|
||||
{ let Latency = 30; }
|
||||
def : WriteRes<VecMul, [Z13_VecMulUnit]> { let Latency = 5; }
|
||||
def : WriteRes<VecStr, [Z13_VecStrUnit]> { let Latency = 4; }
|
||||
def : WriteRes<VecXsPm, [Z13_VecXsPmUnit]> { let Latency = 3; }
|
||||
def : WriteRes<VBU, [Z13_VBUnit]>; // Virtual Branching Unit
|
||||
|
||||
// -------------------------- INSTRUCTIONS ---------------------------------- //
|
||||
|
||||
// InstRW constructs have been used in order to preserve the
|
||||
// readability of the InstrInfo files.
|
||||
|
||||
// For each instruction, as matched by a regexp, provide a list of
|
||||
// resources that it needs. These will be combined into a SchedClass.
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Stack allocation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Control flow instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Return
|
||||
def : InstRW<[FXb, EndGroup], (instregex "Return$")>;
|
||||
def : InstRW<[FXb], (instregex "CondReturn$")>;
|
||||
|
||||
// Compare and branch
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?C(I|R)J$")>;
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?CG(I|R)J$")>;
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?CL(I|R)J$")>;
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?CLG(I|R)J$")>;
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?CG(R|I)J$")>;
|
||||
def : InstRW<[FXb], (instregex "CLR$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "(Asm.*)?CIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "(Asm.*)?CLIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "(Asm.*)?CLGIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "(Asm.*)?CGIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "(Asm.*)?CGRB(Call|Return)?$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "(Asm.*)?CLGRB(Call|Return)?$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "CLR(Call|Return)?$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "(Asm.*)?CLRB(Call|Return)?$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "(Asm.*)?CRB(Call|Return)?$")>;
|
||||
|
||||
// Branch
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?BR$")>;
|
||||
def : InstRW<[FXb], (instregex "(Asm)?BC(R)?$")>;
|
||||
def : InstRW<[VBU], (instregex "(Asm)?BRC(L)?$")>;
|
||||
def : InstRW<[FXa, EndGroup], (instregex "BRCT(G)?$")>;
|
||||
def : InstRW<[VBU], (instregex "(Asm.*)?JG$")>;
|
||||
def : InstRW<[VBU], (instregex "J$")>;
|
||||
// (Need to avoid conflict with "(Asm.*)?CG(I|R)J$")
|
||||
def : InstRW<[VBU], (instregex "Asm(EAlt|E|HAlt|HE|H|LAlt|LE|LH|L|NEAlt|NE)J$")>;
|
||||
def : InstRW<[VBU], (instregex "Asm(NHAlt|NHE|NH|NLAlt|NLE|NLH|NL|NO|O)J$")>;
|
||||
def : InstRW<[FXa, FXa, FXb, FXb, Lat4, GroupAlone], (instregex "BRX(H|LE)$")>;
|
||||
|
||||
// Trap
|
||||
def : InstRW<[VBU], (instregex "(Cond)?Trap$")>;
|
||||
|
||||
// Compare and trap
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?C(G)?IT$")>;
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?C(G)?RT$")>;
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?CLG(I|R)T$")>;
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?CLFIT$")>;
|
||||
def : InstRW<[FXb], (instregex "(Asm.*)?CLRT$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Select instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Select pseudo
|
||||
def : InstRW<[FXa], (instregex "Select(32|64|32Mux)$")>;
|
||||
|
||||
// CondStore pseudos
|
||||
def : InstRW<[FXa], (instregex "CondStore16(Inv)?$")>;
|
||||
def : InstRW<[FXa], (instregex "CondStore16Mux(Inv)?$")>;
|
||||
def : InstRW<[FXa], (instregex "CondStore32(Inv)?$")>;
|
||||
def : InstRW<[FXa], (instregex "CondStore64(Inv)?$")>;
|
||||
def : InstRW<[FXa], (instregex "CondStore8(Inv)?$")>;
|
||||
def : InstRW<[FXa], (instregex "CondStore8Mux(Inv)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Call instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VBU, FXa, FXa, Lat3, GroupAlone], (instregex "BRAS$")>;
|
||||
def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "(Call)?BASR$")>;
|
||||
def : InstRW<[FXb], (instregex "CallB(C)?R$")>;
|
||||
def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "(Call)?BRASL$")>;
|
||||
def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
|
||||
def : InstRW<[VBU], (instregex "CallBRCL$")>;
|
||||
def : InstRW<[VBU], (instregex "CallJG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Move instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Moves
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "MVI(Y)?$")>;
|
||||
|
||||
// Move character
|
||||
def : InstRW<[FXb, LSU, LSU, LSU, Lat8, GroupAlone], (instregex "MVC$")>;
|
||||
|
||||
// Pseudo -> reg move
|
||||
def : InstRW<[FXa], (instregex "COPY(_TO_REGCLASS)?$")>;
|
||||
def : InstRW<[FXa], (instregex "EXTRACT_SUBREG$")>;
|
||||
def : InstRW<[FXa], (instregex "INSERT_SUBREG$")>;
|
||||
def : InstRW<[FXa], (instregex "REG_SEQUENCE$")>;
|
||||
def : InstRW<[FXa], (instregex "SUBREG_TO_REG$")>;
|
||||
|
||||
// Loads
|
||||
def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux|CBB)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LG(RL)?$")>;
|
||||
def : InstRW<[LSU], (instregex "L128$")>;
|
||||
|
||||
def : InstRW<[FXa], (instregex "LLIH(F|H|L)$")>;
|
||||
def : InstRW<[FXa], (instregex "LLIL(F|H|L)$")>;
|
||||
|
||||
def : InstRW<[FXa], (instregex "LG(F|H)I$")>;
|
||||
def : InstRW<[FXa], (instregex "LHI(Mux)?$")>;
|
||||
def : InstRW<[FXa], (instregex "LR(Mux)?$")>;
|
||||
|
||||
// Load and test
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "LT(G)?$")>;
|
||||
def : InstRW<[FXa], (instregex "LT(G)?R$")>;
|
||||
|
||||
// Load on condition
|
||||
def : InstRW<[FXa, LSU, Lat6], (instregex "(Asm.*)?LOC(G)?$")>;
|
||||
def : InstRW<[FXa, Lat2], (instregex "(Asm.*)?LOC(G)?R$")>;
|
||||
def : InstRW<[FXa, Lat2], (instregex "(Asm.*)?LOC(G)?HI$")>;
|
||||
|
||||
// Stores
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "STG(RL)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "ST128$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
|
||||
|
||||
// Store on condition
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "(Asm.*)?STOC(G)?$")>;
|
||||
|
||||
// String moves.
|
||||
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Sign extensions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa], (instregex "L(B|H|G)R$")>;
|
||||
def : InstRW<[FXa], (instregex "LG(B|H|F)R$")>;
|
||||
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "LTGF$")>;
|
||||
def : InstRW<[FXa], (instregex "LTGFR$")>;
|
||||
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "LH(Y)?$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "LG(B|H|F)$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "LG(H|F)RL$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Zero extensions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa], (instregex "LLCR(Mux)?$")>;
|
||||
def : InstRW<[FXa], (instregex "LLHR(Mux)?$")>;
|
||||
def : InstRW<[FXa], (instregex "LLG(C|H|F)R$")>;
|
||||
def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "LL(C|H)H$")>;
|
||||
def : InstRW<[LSU], (instregex "LLHRL$")>;
|
||||
def : InstRW<[LSU], (instregex "LLG(C|H|F|HRL|FRL)$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Truncations
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Multi-register moves
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load multiple (estimated average of 5 ops)
|
||||
def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
|
||||
(instregex "LM(H|Y|G)?$")>;
|
||||
|
||||
// Store multiple (estimated average of ceil(5/2) FXb ops)
|
||||
def : InstRW<[LSU, LSU, FXb, FXb, FXb, Lat10,
|
||||
GroupAlone], (instregex "STM(G|H|Y)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Byte swaps
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa], (instregex "LRV(G)?R$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "LRV(G|H)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "STRV(G|H)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Load address instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa], (instregex "LA(Y|RL)?$")>;
|
||||
|
||||
// Load the Global Offset Table address ( -> larl )
|
||||
def : InstRW<[FXa], (instregex "GOT$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Absolute and Negation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa, Lat2], (instregex "LP(G)?R$")>;
|
||||
def : InstRW<[FXa, FXa, Lat3, BeginGroup], (instregex "L(N|P)GFR$")>;
|
||||
def : InstRW<[FXa, Lat2], (instregex "LN(R|GR)$")>;
|
||||
def : InstRW<[FXa], (instregex "LC(R|GR)$")>;
|
||||
def : InstRW<[FXa, FXa, Lat2, BeginGroup], (instregex "LCGFR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Insertion
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "IC(Y)?$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "IC32(Y)?$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "II(F|H|L)Mux$")>;
|
||||
def : InstRW<[FXa], (instregex "IIHF(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "IIHH(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "IIHL(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "IILF(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "IILH(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "IILL(64)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Addition
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "A(Y)?$")>;
|
||||
def : InstRW<[FXa, LSU, Lat6], (instregex "AH(Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "AIH$")>;
|
||||
def : InstRW<[FXa], (instregex "AFI(Mux)?$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "AG$")>;
|
||||
def : InstRW<[FXa], (instregex "AGFI$")>;
|
||||
def : InstRW<[FXa], (instregex "AGHI(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "AGR(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "AHI(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "AHIMux(K)?$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "AL(Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "AL(FI|HSIK)$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "ALG(F)?$")>;
|
||||
def : InstRW<[FXa], (instregex "ALGHSIK$")>;
|
||||
def : InstRW<[FXa], (instregex "ALGF(I|R)$")>;
|
||||
def : InstRW<[FXa], (instregex "ALGR(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "ALR(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "AR(K)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "A(G)?SI$")>;
|
||||
|
||||
// Logical addition with carry
|
||||
def : InstRW<[FXa, LSU, Lat6, GroupAlone], (instregex "ALC(G)?$")>;
|
||||
def : InstRW<[FXa, Lat2, GroupAlone], (instregex "ALC(G)?R$")>;
|
||||
|
||||
// Add with sign extension (32 -> 64)
|
||||
def : InstRW<[FXa, LSU, Lat6], (instregex "AGF$")>;
|
||||
def : InstRW<[FXa, Lat2], (instregex "AGFR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtraction
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "S(G|Y)?$")>;
|
||||
def : InstRW<[FXa, LSU, Lat6], (instregex "SH(Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "SGR(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "SLFI$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "SLGF(I|R)$")>;
|
||||
def : InstRW<[FXa], (instregex "SLGR(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "SLR(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "SR(K)?$")>;
|
||||
|
||||
// Subtraction with borrow
|
||||
def : InstRW<[FXa, LSU, Lat6, GroupAlone], (instregex "SLB(G)?$")>;
|
||||
def : InstRW<[FXa, Lat2, GroupAlone], (instregex "SLB(G)?R$")>;
|
||||
|
||||
// Subtraction with sign extension (32 -> 64)
|
||||
def : InstRW<[FXa, LSU, Lat6], (instregex "SGF$")>;
|
||||
def : InstRW<[FXa, Lat2], (instregex "SGFR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// AND
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "N(G|Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "NGR(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "NI(FMux|HMux|LMux)$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "NI(Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "NIHF(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "NIHH(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "NIHL(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "NILF(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "NILH(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "NILL(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "NR(K)?$")>;
|
||||
def : InstRW<[LSU, LSU, FXb, Lat9, BeginGroup], (instregex "NC$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// OR
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "O(G|Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "OGR(K)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "OI(Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "OI(FMux|HMux|LMux)$")>;
|
||||
def : InstRW<[FXa], (instregex "OIHF(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "OIHH(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "OIHL(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "OILF(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "OILH(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "OILL(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "OR(K)?$")>;
|
||||
def : InstRW<[LSU, LSU, FXb, Lat9, BeginGroup], (instregex "OC$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// XOR
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "X(G|Y)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "XI(Y)?$")>;
|
||||
def : InstRW<[FXa], (instregex "XIFMux$")>;
|
||||
def : InstRW<[FXa], (instregex "XGR(K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "XIHF(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "XILF(64)?$")>;
|
||||
def : InstRW<[FXa], (instregex "XR(K)?$")>;
|
||||
def : InstRW<[LSU, LSU, FXb, Lat9, BeginGroup], (instregex "XC$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Multiplication
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
|
||||
def : InstRW<[FXa, Lat6], (instregex "MS(R|FI)$")>;
|
||||
def : InstRW<[FXa, LSU, Lat12], (instregex "MSG$")>;
|
||||
def : InstRW<[FXa, Lat8], (instregex "MSGR$")>;
|
||||
def : InstRW<[FXa, Lat6], (instregex "MSGF(I|R)$")>;
|
||||
def : InstRW<[FXa, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
|
||||
def : InstRW<[FXa, Lat9, GroupAlone], (instregex "MLGR$")>;
|
||||
def : InstRW<[FXa, Lat5], (instregex "MGHI$")>;
|
||||
def : InstRW<[FXa, Lat5], (instregex "MHI$")>;
|
||||
def : InstRW<[FXa, LSU, Lat9], (instregex "MH(Y)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Division and remainder
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa, Lat30, GroupAlone], (instregex "DSG(F)?R$")>;
|
||||
def : InstRW<[LSU, FXa, Lat30, GroupAlone], (instregex "DSG(F)?$")>;
|
||||
def : InstRW<[FXa, FXa, Lat20, GroupAlone], (instregex "DLR$")>;
|
||||
def : InstRW<[FXa, FXa, Lat30, GroupAlone], (instregex "DLGR$")>;
|
||||
def : InstRW<[FXa, FXa, LSU, Lat30, GroupAlone], (instregex "DL(G)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Shifts
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa], (instregex "SLL(G|K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "SRL(G|K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "SRA(G|K)?$")>;
|
||||
def : InstRW<[FXa], (instregex "SLA(K)?$")>;
|
||||
|
||||
// Rotate
|
||||
def : InstRW<[FXa, LSU, Lat6], (instregex "RLL(G)?$")>;
|
||||
|
||||
// Rotate and insert
|
||||
def : InstRW<[FXa], (instregex "RISBG(N|32)?$")>;
|
||||
def : InstRW<[FXa], (instregex "RISBH(G|H|L)$")>;
|
||||
def : InstRW<[FXa], (instregex "RISBL(G|H|L)$")>;
|
||||
def : InstRW<[FXa], (instregex "RISBMux$")>;
|
||||
|
||||
// Rotate and Select
|
||||
def : InstRW<[FXa, FXa, Lat3, BeginGroup], (instregex "R(N|O|X)SBG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Comparison
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
|
||||
def : InstRW<[FXb], (instregex "CFI(Mux)?$")>;
|
||||
def : InstRW<[FXb], (instregex "CG(F|H)I$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
|
||||
def : InstRW<[FXb], (instregex "C(G)?R$")>;
|
||||
def : InstRW<[FXb], (instregex "C(HI|IH)$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "CH(F|SI)$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
|
||||
def : InstRW<[FXb], (instregex "CLFI(Mux)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "CLGF(RL)?$")>;
|
||||
def : InstRW<[FXb], (instregex "CLGF(I|R)$")>;
|
||||
def : InstRW<[FXb], (instregex "CLGR$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "CLGRL$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
|
||||
def : InstRW<[FXb], (instregex "CLIH$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "CLI(Y)?$")>;
|
||||
def : InstRW<[FXb], (instregex "CLR$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "CLRL$")>;
|
||||
|
||||
// Compare halfword
|
||||
def : InstRW<[FXb, LSU, Lat6], (instregex "CH(Y|RL)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat6], (instregex "CGH(RL)?$")>;
|
||||
def : InstRW<[FXa, FXb, LSU, Lat6, BeginGroup], (instregex "CHHSI$")>;
|
||||
|
||||
// Compare with sign extension (32 -> 64)
|
||||
def : InstRW<[FXb, LSU, Lat6], (instregex "CGF(RL)?$")>;
|
||||
def : InstRW<[FXb, Lat2], (instregex "CGFR$")>;
|
||||
|
||||
// Compare logical character
|
||||
def : InstRW<[FXb, LSU, LSU, Lat9, BeginGroup], (instregex "CLC$")>;
|
||||
|
||||
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
|
||||
|
||||
// Test under mask
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "TM(Y)?$")>;
|
||||
def : InstRW<[FXb], (instregex "TM(H|L)Mux$")>;
|
||||
def : InstRW<[FXb], (instregex "TMHH(64)?$")>;
|
||||
def : InstRW<[FXb], (instregex "TMHL(64)?$")>;
|
||||
def : InstRW<[FXb], (instregex "TMLH(64)?$")>;
|
||||
def : InstRW<[FXb], (instregex "TMLL(64)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Prefetch
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[LSU], (instregex "PFD(RL)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Atomic operations
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXb, EndGroup], (instregex "Serialize$")>;
|
||||
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "LAA(G)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "LAAL(G)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "LAN(G)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "LAO(G)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "LAX(G)?$")>;
|
||||
|
||||
// Compare and swap
|
||||
def : InstRW<[FXa, FXb, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Transactional execution
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Transaction begin
|
||||
def : InstRW<[LSU, LSU, FXb, FXb, FXb, FXb, FXb, Lat15, GroupAlone],
|
||||
(instregex "TBEGIN(C|_nofloat)?$")>;
|
||||
|
||||
// Transaction end
|
||||
def : InstRW<[FXb, GroupAlone], (instregex "TEND$")>;
|
||||
|
||||
// Transaction abort
|
||||
def : InstRW<[LSU, GroupAlone], (instregex "TABORT$")>;
|
||||
|
||||
// Extract Transaction Nesting Depth
|
||||
def : InstRW<[FXa], (instregex "ETND$")>;
|
||||
|
||||
// Nontransactional store
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "NTSTG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Processor assist
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXb], (instregex "PPA$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Miscellaneous Instructions.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Insert Program Mask
|
||||
def : InstRW<[FXa, Lat3, EndGroup], (instregex "IPM$")>;
|
||||
|
||||
// Extract access register
|
||||
def : InstRW<[LSU], (instregex "EAR$")>;
|
||||
|
||||
// Find leftmost one
|
||||
def : InstRW<[FXa, Lat6, GroupAlone], (instregex "FLOGR$")>;
|
||||
|
||||
// Population count
|
||||
def : InstRW<[FXa, Lat3], (instregex "POPCNT$")>;
|
||||
|
||||
// Extend
|
||||
def : InstRW<[FXa], (instregex "AEXT128_64$")>;
|
||||
def : InstRW<[FXa], (instregex "ZEXT128_(32|64)$")>;
|
||||
|
||||
// String instructions
|
||||
def : InstRW<[FXa, LSU, Lat30], (instregex "SRST$")>;
|
||||
|
||||
// Move with key
|
||||
def : InstRW<[FXa, FXa, FXb, LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
|
||||
|
||||
// Extract CPU Time
|
||||
def : InstRW<[FXa, Lat5, LSU], (instregex "ECTG$")>;
|
||||
|
||||
// Execute
|
||||
def : InstRW<[FXb, GroupAlone], (instregex "EX(RL)?$")>;
|
||||
|
||||
// Program return
|
||||
def : InstRW<[FXb, Lat30], (instregex "PR$")>;
|
||||
|
||||
// Inline assembly
|
||||
def : InstRW<[LSU, LSU, LSU, FXa, FXa, FXb, Lat9, GroupAlone],
|
||||
(instregex "STCK(F)?$")>;
|
||||
def : InstRW<[LSU, LSU, LSU, LSU, FXa, FXa, FXb, FXb, Lat11, GroupAlone],
|
||||
(instregex "STCKE$")>;
|
||||
def : InstRW<[FXa, LSU, Lat5], (instregex "STFLE$")>;
|
||||
def : InstRW<[FXb, Lat30], (instregex "SVC$")>;
|
||||
|
||||
// Store real address
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "STRAG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// .insn directive instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// An "empty" sched-class will be assigned instead of the "invalid sched-class".
|
||||
// getNumDecoderSlots() will then return 1 instead of 0.
|
||||
def : InstRW<[], (instregex "Insn.*")>;
|
||||
|
||||
|
||||
// ----------------------------- Floating point ----------------------------- //
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Select instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXa], (instregex "SelectF(32|64|128)$")>;
|
||||
def : InstRW<[FXa], (instregex "CondStoreF32(Inv)?$")>;
|
||||
def : InstRW<[FXa], (instregex "CondStoreF64(Inv)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Move instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load zero
|
||||
def : InstRW<[FXb], (instregex "LZ(DR|ER)$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, BeginGroup], (instregex "LZXR$")>;
|
||||
|
||||
// Load
|
||||
def : InstRW<[VecXsPm], (instregex "LER$")>;
|
||||
def : InstRW<[FXb], (instregex "LD(R|R32|GR)$")>;
|
||||
def : InstRW<[FXb, Lat3], (instregex "LGDR$")>;
|
||||
def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "LXR$")>;
|
||||
|
||||
// Load and Test
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "LT(D|E)BR$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare(_VecPseudo)?$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare(_VecPseudo)?$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "LTXBR$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat11, GroupAlone],
|
||||
(instregex "LTXBRCompare(_VecPseudo)?$")>;
|
||||
|
||||
// Copy sign
|
||||
def : InstRW<[VecXsPm], (instregex "CPSDRd(d|s)$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "CPSDRs(d|s)$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Load instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VecXsPm, LSU, Lat7], (instregex "LE(Y)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LX$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Store instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXb, LSU, Lat7], (instregex "STD(Y)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat7], (instregex "STE(Y)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat5], (instregex "STX$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Conversion instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load rounded
|
||||
def : InstRW<[VecBF], (instregex "LEDBR(A)?$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat20], (instregex "LEXBR(A)?$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat20], (instregex "LDXBR(A)?$")>;
|
||||
|
||||
// Load lengthened
|
||||
def : InstRW<[VecBF, LSU, Lat12], (instregex "LDEB$")>;
|
||||
def : InstRW<[VecBF], (instregex "LDEBR$")>;
|
||||
def : InstRW<[VecBF, VecBF, LSU, Lat12 , GroupAlone], (instregex "LX(D|E)B$")>;
|
||||
def : InstRW<[VecBF, VecBF, Lat9 , GroupAlone], (instregex "LX(D|E)BR$")>;
|
||||
|
||||
// Convert from fixed / logical
|
||||
def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CE(F|G)BR$")>;
|
||||
def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CD(F|G)BR$")>;
|
||||
def : InstRW<[FXb, VecDF, VecDF, Lat12, GroupAlone], (instregex "CX(F|G)BR$")>;
|
||||
def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CEL(F|G)BR$")>;
|
||||
def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CDL(F|G)BR$")>;
|
||||
def : InstRW<[FXb, VecDF, VecDF, Lat12, GroupAlone], (instregex "CXL(F|G)BR$")>;
|
||||
|
||||
// Convert to fixed / logical
|
||||
def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CF(E|D)BR$")>;
|
||||
def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CG(E|D)BR$")>;
|
||||
def : InstRW<[FXb, VecDF, VecDF, Lat20, BeginGroup], (instregex "C(F|G)XBR$")>;
|
||||
def : InstRW<[FXb, VecBF, Lat11, GroupAlone], (instregex "CLFEBR$")>;
|
||||
def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CLFDBR$")>;
|
||||
def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CLG(E|D)BR$")>;
|
||||
def : InstRW<[FXb, VecDF, VecDF, Lat20, BeginGroup], (instregex "CL(F|G)XBR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Unary arithmetic
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load Complement / Negative / Positive
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "L(C|N|P)DBR$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "L(C|N|P)EBR$")>;
|
||||
def : InstRW<[FXb], (instregex "LCDFR(_32)?$")>;
|
||||
def : InstRW<[FXb], (instregex "LNDFR(_32)?$")>;
|
||||
def : InstRW<[FXb], (instregex "LPDFR(_32)?$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "L(C|N|P)XBR$")>;
|
||||
|
||||
// Square root
|
||||
def : InstRW<[VecFPd, LSU], (instregex "SQ(E|D)B$")>;
|
||||
def : InstRW<[VecFPd], (instregex "SQ(E|D)BR$")>;
|
||||
def : InstRW<[VecFPd, VecFPd, GroupAlone], (instregex "SQXBR$")>;
|
||||
|
||||
// Load FP integer
|
||||
def : InstRW<[VecBF], (instregex "FIEBR(A)?$")>;
|
||||
def : InstRW<[VecBF], (instregex "FIDBR(A)?$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "FIXBR(A)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Binary arithmetic
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Addition
|
||||
def : InstRW<[VecBF, LSU, Lat12], (instregex "A(E|D)B$")>;
|
||||
def : InstRW<[VecBF], (instregex "A(E|D)BR$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "AXBR$")>;
|
||||
|
||||
// Subtraction
|
||||
def : InstRW<[VecBF, LSU, Lat12], (instregex "S(E|D)B$")>;
|
||||
def : InstRW<[VecBF], (instregex "S(E|D)BR$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "SXBR$")>;
|
||||
|
||||
// Multiply
|
||||
def : InstRW<[VecBF, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
|
||||
def : InstRW<[VecBF], (instregex "M(D|DE|EE)BR$")>;
|
||||
def : InstRW<[VecBF, VecBF, LSU, Lat12, GroupAlone], (instregex "MXDB$")>;
|
||||
def : InstRW<[VecBF, VecBF, Lat9, GroupAlone], (instregex "MXDBR$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "MXBR$")>;
|
||||
|
||||
// Multiply and add / subtract
|
||||
def : InstRW<[VecBF, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
|
||||
def : InstRW<[VecBF, GroupAlone], (instregex "M(A|S)EBR$")>;
|
||||
def : InstRW<[VecBF, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
|
||||
def : InstRW<[VecBF], (instregex "M(A|S)DBR$")>;
|
||||
|
||||
// Division
|
||||
def : InstRW<[VecFPd, LSU], (instregex "D(E|D)B$")>;
|
||||
def : InstRW<[VecFPd], (instregex "D(E|D)BR$")>;
|
||||
def : InstRW<[VecFPd, VecFPd, GroupAlone], (instregex "DXBR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Comparisons
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Compare
|
||||
def : InstRW<[VecXsPm, LSU, Lat8], (instregex "C(E|D)B$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "C(E|D)BR?$")>;
|
||||
def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "CXBR$")>;
|
||||
|
||||
// Test Data Class
|
||||
def : InstRW<[LSU, VecXsPm, Lat9], (instregex "TC(E|D)B$")>;
|
||||
def : InstRW<[LSU, VecDF, VecDF, Lat15, GroupAlone], (instregex "TCXB$")>;
|
||||
|
||||
|
||||
// --------------------------------- Vector --------------------------------- //
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Move instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXb], (instregex "VLR(32|64)?$")>;
|
||||
def : InstRW<[FXb, Lat4], (instregex "VLGV(B|F|G|H)?$")>;
|
||||
def : InstRW<[FXb], (instregex "VLVG(B|F|G|H)?$")>;
|
||||
def : InstRW<[FXb, Lat2], (instregex "VLVGP(32)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Immediate instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VecXsPm], (instregex "VZERO$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VONE$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VGBM$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VGM(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VLEI(B|F|G|H)$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VREPI(B|F|G|H)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Loads
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[LSU], (instregex "VL(L|BB)?$")>;
|
||||
def : InstRW<[LSU], (instregex "VL(32|64)$")>;
|
||||
def : InstRW<[LSU], (instregex "VLLEZ(B|F|G|H)?$")>;
|
||||
def : InstRW<[LSU], (instregex "VLREP(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm, LSU, Lat7], (instregex "VLE(B|F|G|H)$")>;
|
||||
def : InstRW<[FXb, LSU, VecXsPm, Lat11, BeginGroup], (instregex "VGE(F|G)$")>;
|
||||
def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
|
||||
(instregex "VLM$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Stores
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXb, LSU, Lat8], (instregex "VST(L|32|64)?$")>;
|
||||
def : InstRW<[FXb, LSU, Lat8], (instregex "VSTE(F|G)$")>;
|
||||
def : InstRW<[FXb, LSU, VecXsPm, Lat11, BeginGroup], (instregex "VSTE(B|H)$")>;
|
||||
def : InstRW<[LSU, LSU, FXb, FXb, FXb, FXb, FXb, Lat20, GroupAlone],
|
||||
(instregex "VSTM$")>;
|
||||
def : InstRW<[FXb, FXb, LSU, Lat12, BeginGroup], (instregex "VSCE(F|G)$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Selects and permutes
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VecXsPm], (instregex "VMRH(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VMRL(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VPERM$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VPDI$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VREP(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VSEL$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Widening and narrowing
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VecXsPm], (instregex "VPK(F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VPKS(F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "VPKS(F|G|H)S$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VPKLS(F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "VPKLS(F|G|H)S$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VSEG(B|F|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VUPH(B|F|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VUPL(B|F)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VUPLH(B|F|H|W)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VUPLL(B|F|H)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Integer arithmetic
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VecXsPm], (instregex "VA(B|F|G|H|Q|C|CQ)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VACC(B|F|G|H|Q|C|CQ)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VAVG(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VAVGL(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VN(C|O)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VO$")>;
|
||||
def : InstRW<[VecMul], (instregex "VCKSM$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VCLZ(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VCTZ(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VX$")>;
|
||||
def : InstRW<[VecMul], (instregex "VGFM?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VGFMA(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VGFM(B|F|G|H)$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VLC(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VLP(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VMX(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VMXL(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VMN(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VMNL(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMAL(B|F)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMALE(B|F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMALH(B|F|H|W)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMALO(B|F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMAO(B|F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMAE(B|F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMAH(B|F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VME(B|F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMH(B|F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VML(B|F)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMLE(B|F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMLH(B|F|H|W)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMLO(B|F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VMO(B|F|H)?$")>;
|
||||
|
||||
def : InstRW<[VecXsPm], (instregex "VPOPCT$")>;
|
||||
|
||||
def : InstRW<[VecXsPm], (instregex "VERLL(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VERLLV(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VERIM(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VESL(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VESLV(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VESRA(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VESRAV(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VESRL(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VESRLV(B|F|G|H)?$")>;
|
||||
|
||||
def : InstRW<[VecXsPm], (instregex "VSL(DB)?$")>;
|
||||
def : InstRW<[VecXsPm, VecXsPm, Lat8], (instregex "VSLB$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VSR(A|L)$")>;
|
||||
def : InstRW<[VecXsPm, VecXsPm, Lat8], (instregex "VSR(A|L)B$")>;
|
||||
|
||||
def : InstRW<[VecXsPm], (instregex "VSB(I|IQ|CBI|CBIQ)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VSCBI(B|F|G|H|Q)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VS(F|G|H|Q)?$")>;
|
||||
|
||||
def : InstRW<[VecMul], (instregex "VSUM(B|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VSUMG(F|H)?$")>;
|
||||
def : InstRW<[VecMul], (instregex "VSUMQ(F|G)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Integer comparison
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "VEC(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "VECL(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VCEQ(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "VCEQ(B|F|G|H)S$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VCH(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "VCH(B|F|G|H)S$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VCHL(B|F|G|H)?$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "VCHL(B|F|G|H)S$")>;
|
||||
def : InstRW<[VecStr, Lat5], (instregex "VTM$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Floating-point arithmetic
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VecBF], (instregex "VCD(G|GB|LG|LGB)$")>;
|
||||
def : InstRW<[VecBF], (instregex "WCD(GB|LGB)$")>;
|
||||
def : InstRW<[VecBF], (instregex "VC(L)?GD$")>;
|
||||
def : InstRW<[VecBF], (instregex "(V|W)FADB$")>;
|
||||
def : InstRW<[VecBF], (instregex "(V|W)CGDB$")>;
|
||||
def : InstRW<[VecBF], (instregex "VF(I|M|A|S)$")>;
|
||||
def : InstRW<[VecBF], (instregex "VF(I|M|S)DB$")>;
|
||||
def : InstRW<[VecBF], (instregex "WF(I|M|S)DB$")>;
|
||||
def : InstRW<[VecBF], (instregex "(V|W)CLGDB$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VFL(C|N|P)DB$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "WFL(C|N|P)DB$")>;
|
||||
def : InstRW<[VecBF], (instregex "VFM(A|S)$")>;
|
||||
def : InstRW<[VecBF], (instregex "VFM(A|S)DB$")>;
|
||||
def : InstRW<[VecBF], (instregex "WFM(A|S)DB$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VFPSO$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "(V|W)FPSODB$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "VFTCI(DB)?$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "WFTCIDB$")>;
|
||||
def : InstRW<[VecBF], (instregex "VL(DE|ED)$")>;
|
||||
def : InstRW<[VecBF], (instregex "VL(DE|ED)B$")>;
|
||||
def : InstRW<[VecBF], (instregex "WL(DE|ED)B$")>;
|
||||
|
||||
// divide / square root
|
||||
def : InstRW<[VecFPd], (instregex "VFD$")>;
|
||||
def : InstRW<[VecFPd], (instregex "(V|W)FDDB$")>;
|
||||
def : InstRW<[VecFPd], (instregex "VFSQ$")>;
|
||||
def : InstRW<[VecFPd], (instregex "(V|W)FSQDB$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Floating-point comparison
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VecXsPm], (instregex "VFC(E|H|HE)$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "VFC(E|H|HE)DB$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)$")>;
|
||||
def : InstRW<[VecXsPm], (instregex "WFC(E|H|HE)DB$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "VFC(E|H|HE)DBS$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "WFC(E|H|HE)DBS$")>;
|
||||
def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)DB$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: Floating-point insertion and extraction
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXb], (instregex "LEFR$")>;
|
||||
def : InstRW<[FXb, Lat4], (instregex "LFER$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector: String instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VecStr], (instregex "VFAE(B)?$")>;
|
||||
def : InstRW<[VecStr, Lat5], (instregex "VFAEBS$")>;
|
||||
def : InstRW<[VecStr], (instregex "VFAE(F|H)$")>;
|
||||
def : InstRW<[VecStr, Lat5], (instregex "VFAE(F|H)S$")>;
|
||||
def : InstRW<[VecStr], (instregex "VFAEZ(B|F|H)$")>;
|
||||
def : InstRW<[VecStr, Lat5], (instregex "VFAEZ(B|F|H)S$")>;
|
||||
def : InstRW<[VecStr], (instregex "VFEE(B|F|H|ZB|ZF|ZH)?$")>;
|
||||
def : InstRW<[VecStr, Lat5], (instregex "VFEE(B|F|H|ZB|ZF|ZH)S$")>;
|
||||
def : InstRW<[VecStr], (instregex "VFENE(B|F|H|ZB|ZF|ZH)?$")>;
|
||||
def : InstRW<[VecStr, Lat5], (instregex "VFENE(B|F|H|ZB|ZF|ZH)S$")>;
|
||||
def : InstRW<[VecStr], (instregex "VISTR(B|F|H)?$")>;
|
||||
def : InstRW<[VecStr, Lat5], (instregex "VISTR(B|F|H)S$")>;
|
||||
def : InstRW<[VecStr], (instregex "VSTRC(B|F|H)?$")>;
|
||||
def : InstRW<[VecStr, Lat5], (instregex "VSTRC(B|F|H)S$")>;
|
||||
def : InstRW<[VecStr], (instregex "VSTRCZ(B|F|H)$")>;
|
||||
def : InstRW<[VecStr, Lat5], (instregex "VSTRCZ(B|F|H)S$")>;
|
||||
|
||||
}
|
||||
|
||||
713
lib/Target/SystemZ/SystemZScheduleZ196.td
Normal file
713
lib/Target/SystemZ/SystemZScheduleZ196.td
Normal file
@ -0,0 +1,713 @@
|
||||
//=- SystemZScheduleZ196.td - SystemZ Scheduling Definitions ---*- tblgen -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines the machine model for Z196 to support instruction
|
||||
// scheduling and other instruction cost heuristics.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def Z196Model : SchedMachineModel {
|
||||
|
||||
let IssueWidth = 3; // 3 instructions decoded per cycle.
|
||||
let MicroOpBufferSize = 40; // Issue queues
|
||||
let LoadLatency = 1; // Optimistic load latency.
|
||||
|
||||
let PostRAScheduler = 1;
|
||||
|
||||
// Extra cycles for a mispredicted branch.
|
||||
let MispredictPenalty = 8;
|
||||
}
|
||||
|
||||
let SchedModel = Z196Model in {
|
||||
|
||||
// These definitions could be put in a subtarget common include file,
|
||||
// but it seems the include system in Tablegen currently rejects
|
||||
// multiple includes of same file.
|
||||
def : WriteRes<GroupAlone, []> {
|
||||
let NumMicroOps = 0;
|
||||
let BeginGroup = 1;
|
||||
let EndGroup = 1;
|
||||
}
|
||||
def : WriteRes<EndGroup, []> {
|
||||
let NumMicroOps = 0;
|
||||
let EndGroup = 1;
|
||||
}
|
||||
def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
|
||||
|
||||
// Execution units.
|
||||
def Z196_FXUnit : ProcResource<1>;
|
||||
def Z196_LSUnit : ProcResource<1>;
|
||||
def Z196_FPUnit : ProcResource<1>;
|
||||
|
||||
// Subtarget specific definitions of scheduling resources.
|
||||
def : WriteRes<FXU, [Z196_FXUnit]> { let Latency = 1; }
|
||||
def : WriteRes<LSU, [Z196_LSUnit]> { let Latency = 4; }
|
||||
def : WriteRes<LSU_lat1, [Z196_LSUnit]> { let Latency = 1; }
|
||||
def : WriteRes<FPU, [Z196_FPUnit]> { let Latency = 8; }
|
||||
|
||||
// -------------------------- INSTRUCTIONS ---------------------------------- //
|
||||
|
||||
// InstRW constructs have been used in order to preserve the
|
||||
// readability of the InstrInfo files.
|
||||
|
||||
// For each instruction, as matched by a regexp, provide a list of
|
||||
// resources that it needs. These will be combined into a SchedClass.
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Stack allocation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Control flow instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Return
|
||||
def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
|
||||
def : InstRW<[LSU_lat1, EndGroup], (instregex "CondReturn$")>;
|
||||
|
||||
// Compare and branch
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?C(I|R)J$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CG(I|R)J$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CL(I|R)J$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CLG(I|R)J$")>;
|
||||
def : InstRW<[FXU], (instregex "CLR$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CLIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CLGIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CGIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CGRB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CLGRB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "CLR(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CLRB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CRB(Call|Return)?$")>;
|
||||
|
||||
// Branch
|
||||
def : InstRW<[LSU, EndGroup], (instregex "(Asm.*)?BR$")>;
|
||||
def : InstRW<[LSU, EndGroup], (instregex "(Asm)?BC(R)?$")>;
|
||||
def : InstRW<[LSU, EndGroup], (instregex "(Asm)?BRC(L)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BRCT(G)?$")>;
|
||||
def : InstRW<[LSU, EndGroup], (instregex "(Asm.*)?JG$")>;
|
||||
def : InstRW<[LSU, EndGroup], (instregex "J$")>;
|
||||
// (Need to avoid conflict with "(Asm.*)?CG(I|R)J$")
|
||||
def : InstRW<[LSU, EndGroup], (instregex "Asm(EAlt|E|HAlt|HE|H|LAlt|LE|LH|L|NEAlt|NE)J$")>;
|
||||
def : InstRW<[LSU, EndGroup], (instregex "Asm(NHAlt|NHE|NH|NLAlt|NLE|NLH|NL|NO|O)J$")>;
|
||||
def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone], (instregex "BRX(H|LE)$")>;
|
||||
|
||||
// Trap
|
||||
def : InstRW<[LSU, EndGroup], (instregex "(Cond)?Trap$")>;
|
||||
|
||||
// Compare and trap
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?C(G)?IT$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?C(G)?RT$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CLG(I|R)T$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CLFIT$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CLRT$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Select instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Select pseudo
|
||||
def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
|
||||
|
||||
// CondStore pseudos
|
||||
def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Call instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "BRAS$")>;
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BASR$")>;
|
||||
def : InstRW<[LSU, EndGroup], (instregex "CallB(C)?R$")>;
|
||||
def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
|
||||
def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
|
||||
def : InstRW<[LSU, EndGroup], (instregex "CallBRCL$")>;
|
||||
def : InstRW<[LSU, EndGroup], (instregex "CallJG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Move instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Moves
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
|
||||
|
||||
// Move character
|
||||
def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
|
||||
|
||||
// Pseudo -> reg move
|
||||
def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
|
||||
def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
|
||||
def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
|
||||
def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
|
||||
def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
|
||||
|
||||
// Loads
|
||||
def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LG(RL)?$")>;
|
||||
def : InstRW<[LSU], (instregex "L128$")>;
|
||||
|
||||
def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
|
||||
def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
|
||||
|
||||
def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
|
||||
def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
|
||||
|
||||
// Load and test
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LT(G)?R$")>;
|
||||
|
||||
// Load on condition
|
||||
def : InstRW<[FXU, LSU, Lat6, EndGroup], (instregex "(Asm.*)?LOC(G)?$")>;
|
||||
def : InstRW<[FXU, Lat2, EndGroup], (instregex "(Asm.*)?LOC(G)?R$")>;
|
||||
|
||||
// Stores
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
|
||||
|
||||
// Store on condition
|
||||
def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "(Asm.*)?STOC(G)?$")>;
|
||||
|
||||
// String moves.
|
||||
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Sign extensions
|
||||
//===----------------------------------------------------------------------===//
|
||||
def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
|
||||
def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
|
||||
def : InstRW<[FXU], (instregex "LTGFR$")>;
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Zero extensions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LLG(C|F|H)R$")>;
|
||||
def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
|
||||
def : InstRW<[LSU], (instregex "LLHRL$")>;
|
||||
def : InstRW<[LSU], (instregex "LLG(C|F|H|FRL|HRL)$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Truncations
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Multi-register moves
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load multiple (estimated average of 5 ops)
|
||||
def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
|
||||
(instregex "LM(H|Y|G)?$")>;
|
||||
|
||||
// Store multiple (estimated average of 3 ops)
|
||||
def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
|
||||
(instregex "STM(H|Y|G)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Byte swaps
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Load address instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
|
||||
|
||||
// Load the Global Offset Table address
|
||||
def : InstRW<[FXU], (instregex "GOT$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Absolute and Negation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
|
||||
def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
|
||||
def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
|
||||
def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
|
||||
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Insertion
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
|
||||
def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IILF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IILH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IILL(64)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Addition
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AH(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AIH$")>;
|
||||
def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AGFI$")>;
|
||||
def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AHI(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
|
||||
def : InstRW<[FXU], (instregex "ALGHSIK$")>;
|
||||
def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
|
||||
def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "ALR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AR(K)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
|
||||
|
||||
// Logical addition with carry
|
||||
def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
|
||||
def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
|
||||
|
||||
// Add with sign extension (32 -> 64)
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AGF$")>;
|
||||
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "AGFR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtraction
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SH(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SLFI$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
|
||||
def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SLR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SR(K)?$")>;
|
||||
|
||||
// Subtraction with borrow
|
||||
def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
|
||||
def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
|
||||
|
||||
// Subtraction with sign extension (32 -> 64)
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SGF$")>;
|
||||
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "SGFR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// AND
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NILF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NILH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NILL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NR(K)?$")>;
|
||||
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// OR
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OGR(K)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
|
||||
def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OILF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OILH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OILL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OR(K)?$")>;
|
||||
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// XOR
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "XIFMux$")>;
|
||||
def : InstRW<[FXU], (instregex "XGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "XILF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "XR(K)?$")>;
|
||||
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Multiplication
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
|
||||
def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
|
||||
def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
|
||||
def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
|
||||
def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
|
||||
def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
|
||||
def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
|
||||
def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Division and remainder
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FPU, FPU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
||||
(instregex "DSG(F)?R$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
|
||||
(instregex "DSG(F)?$")>;
|
||||
def : InstRW<[FPU, FPU, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
||||
(instregex "DL(G)?R$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
||||
(instregex "DL(G)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Shifts
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
|
||||
def : InstRW<[FXU, Lat2], (instregex "SLA(K)?$")>;
|
||||
|
||||
// Rotate
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
|
||||
|
||||
// Rotate and insert
|
||||
def : InstRW<[FXU], (instregex "RISBG(32)?$")>;
|
||||
def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
|
||||
def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
|
||||
def : InstRW<[FXU], (instregex "RISBMux$")>;
|
||||
|
||||
// Rotate and Select
|
||||
def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Comparison
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CFI(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
|
||||
def : InstRW<[FXU], (instregex "C(G)?R$")>;
|
||||
def : InstRW<[FXU], (instregex "C(HI|IH)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
|
||||
def : InstRW<[FXU], (instregex "CLGR$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
|
||||
def : InstRW<[FXU], (instregex "CLIH$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CLR$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
|
||||
|
||||
// Compare halfword
|
||||
def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CH(Y|RL)?$")>;
|
||||
def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CGH(RL)?$")>;
|
||||
def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CHHSI$")>;
|
||||
|
||||
// Compare with sign extension (32 -> 64)
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, Lat2, GroupAlone], (instregex "CGF(RL)?$")>;
|
||||
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "CGFR$")>;
|
||||
|
||||
// Compare logical character
|
||||
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "CLC$")>;
|
||||
|
||||
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
|
||||
|
||||
// Test under mask
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
|
||||
def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Prefetch
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[LSU, GroupAlone], (instregex "PFD(RL)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Atomic operations
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
|
||||
|
||||
// Compare and swap
|
||||
def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Miscellaneous Instructions.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Insert Program Mask
|
||||
def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
|
||||
|
||||
// Extract access register
|
||||
def : InstRW<[LSU], (instregex "EAR$")>;
|
||||
|
||||
// Find leftmost one
|
||||
def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
|
||||
|
||||
// Population count
|
||||
def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
|
||||
|
||||
// Extend
|
||||
def : InstRW<[FXU], (instregex "AEXT128_64$")>;
|
||||
def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
|
||||
|
||||
// String instructions
|
||||
def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
|
||||
|
||||
// Move with key
|
||||
def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
|
||||
|
||||
// Extract CPU Time
|
||||
def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
|
||||
|
||||
// Execute
|
||||
def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
|
||||
|
||||
// Program return
|
||||
def : InstRW<[FXU, Lat30], (instregex "PR$")>;
|
||||
|
||||
// Inline assembly
|
||||
def : InstRW<[FXU, LSU, Lat15], (instregex "STCK$")>;
|
||||
def : InstRW<[FXU, LSU, Lat12], (instregex "STCKF$")>;
|
||||
def : InstRW<[LSU, FXU, Lat5], (instregex "STCKE$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
|
||||
def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
|
||||
|
||||
// Store real address
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// .insn directive instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// An "empty" sched-class will be assigned instead of the "invalid sched-class".
|
||||
// getNumDecoderSlots() will then return 1 instead of 0.
|
||||
def : InstRW<[], (instregex "Insn.*")>;
|
||||
|
||||
|
||||
// ----------------------------- Floating point ----------------------------- //
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Select instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Move instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load zero
|
||||
def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
|
||||
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
|
||||
|
||||
// Load
|
||||
def : InstRW<[FXU], (instregex "LER$")>;
|
||||
def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
|
||||
def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
|
||||
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
|
||||
|
||||
// Load and Test
|
||||
def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
|
||||
def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
|
||||
def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat9, GroupAlone], (instregex "LTXBR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat9, GroupAlone],
|
||||
(instregex "LTXBRCompare(_VecPseudo)?$")>;
|
||||
|
||||
// Copy sign
|
||||
def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
|
||||
def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Load instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[LSU], (instregex "LE(Y)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LX$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Store instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Conversion instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load rounded
|
||||
def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
|
||||
|
||||
// Load lengthened
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
|
||||
def : InstRW<[FPU], (instregex "LDEBR$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
|
||||
def : InstRW<[FPU, FPU, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
|
||||
|
||||
// Convert from fixed / logical
|
||||
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, FPU, Lat11, GroupAlone], (instregex "CX(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, FPU, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
|
||||
|
||||
// Convert to fixed / logical
|
||||
def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR$")>;
|
||||
def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
|
||||
def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Unary arithmetic
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load Complement / Negative / Positive
|
||||
def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
|
||||
def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
|
||||
def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
|
||||
|
||||
// Square root
|
||||
def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
|
||||
def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "SQXBR$")>;
|
||||
|
||||
// Load FP integer
|
||||
def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
|
||||
def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Binary arithmetic
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Addition
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
|
||||
def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat20, GroupAlone], (instregex "AXBR$")>;
|
||||
|
||||
// Subtraction
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
|
||||
def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat20, GroupAlone], (instregex "SXBR$")>;
|
||||
|
||||
// Multiply
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
|
||||
def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
|
||||
def : InstRW<[FPU, FPU, Lat10, GroupAlone], (instregex "MXDBR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "MXBR$")>;
|
||||
|
||||
// Multiply and add / subtract
|
||||
def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
|
||||
def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
|
||||
def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
|
||||
def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
|
||||
|
||||
// Division
|
||||
def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
|
||||
def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "DXBR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Comparisons
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Compare
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
|
||||
def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
|
||||
|
||||
// Test Data Class
|
||||
def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
|
||||
|
||||
}
|
||||
|
||||
743
lib/Target/SystemZ/SystemZScheduleZEC12.td
Normal file
743
lib/Target/SystemZ/SystemZScheduleZEC12.td
Normal file
@ -0,0 +1,743 @@
|
||||
//=- SystemZScheduleZEC12.td - SystemZ Scheduling Definitions --*- tblgen -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines the machine model for ZEC12 to support instruction
|
||||
// scheduling and other instruction cost heuristics.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def ZEC12Model : SchedMachineModel {
|
||||
|
||||
let IssueWidth = 3; // 3 instructions decoded per cycle.
|
||||
let MicroOpBufferSize = 40; // Issue queues
|
||||
let LoadLatency = 1; // Optimistic load latency.
|
||||
|
||||
let PostRAScheduler = 1;
|
||||
|
||||
// Extra cycles for a mispredicted branch.
|
||||
let MispredictPenalty = 8;
|
||||
}
|
||||
|
||||
let SchedModel = ZEC12Model in {
|
||||
|
||||
// These definitions could be put in a subtarget common include file,
|
||||
// but it seems the include system in Tablegen currently rejects
|
||||
// multiple includes of same file.
|
||||
def : WriteRes<GroupAlone, []> {
|
||||
let NumMicroOps = 0;
|
||||
let BeginGroup = 1;
|
||||
let EndGroup = 1;
|
||||
}
|
||||
def : WriteRes<EndGroup, []> {
|
||||
let NumMicroOps = 0;
|
||||
let EndGroup = 1;
|
||||
}
|
||||
def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
|
||||
def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
|
||||
|
||||
// Execution units.
|
||||
def ZEC12_VBUnit : ProcResource<1>;
|
||||
def ZEC12_FXUnit : ProcResource<1>;
|
||||
def ZEC12_LSUnit : ProcResource<1>;
|
||||
def ZEC12_FPUnit : ProcResource<1>;
|
||||
|
||||
// Subtarget specific definitions of scheduling resources.
|
||||
def : WriteRes<FXU, [ZEC12_FXUnit]> { let Latency = 1; }
|
||||
def : WriteRes<LSU, [ZEC12_LSUnit]> { let Latency = 4; }
|
||||
def : WriteRes<LSU_lat1, [ZEC12_LSUnit]> { let Latency = 1; }
|
||||
def : WriteRes<FPU, [ZEC12_FPUnit]> { let Latency = 8; }
|
||||
def : WriteRes<VBU, [ZEC12_VBUnit]>; // Virtual Branching Unit
|
||||
|
||||
// -------------------------- INSTRUCTIONS ---------------------------------- //
|
||||
|
||||
// InstRW constructs have been used in order to preserve the
|
||||
// readability of the InstrInfo files.
|
||||
|
||||
// For each instruction, as matched by a regexp, provide a list of
|
||||
// resources that it needs. These will be combined into a SchedClass.
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Stack allocation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Control flow instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Return
|
||||
def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
|
||||
def : InstRW<[LSU_lat1], (instregex "CondReturn$")>;
|
||||
|
||||
// Compare and branch
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?C(I|R)J$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CG(I|R)J$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CL(I|R)J$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CLG(I|R)J$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CG(R|I)J$")>;
|
||||
def : InstRW<[FXU], (instregex "CLR$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CLIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CLGIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CGIB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CGRB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CLGRB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "CLR(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CLRB(Call|Return)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "(Asm.*)?CRB(Call|Return)?$")>;
|
||||
|
||||
// Branch
|
||||
def : InstRW<[LSU, Lat4], (instregex "(Asm.*)?BR$")>;
|
||||
def : InstRW<[LSU, Lat4], (instregex "(Asm)?BC(R)?$")>;
|
||||
def : InstRW<[VBU], (instregex "(Asm)?BRC(L)?$")>;
|
||||
def : InstRW<[FXU, EndGroup], (instregex "BRCT(G)?$")>;
|
||||
def : InstRW<[VBU], (instregex "(Asm.*)?JG$")>;
|
||||
def : InstRW<[VBU], (instregex "J$")>;
|
||||
// (Need to avoid conflict with "(Asm.*)?CG(I|R)J$")
|
||||
def : InstRW<[VBU], (instregex "Asm(EAlt|E|HAlt|HE|H|LAlt|LE|LH|L|NEAlt|NE)J$")>;
|
||||
def : InstRW<[VBU], (instregex "Asm(NHAlt|NHE|NH|NLAlt|NLE|NLH|NL|NO|O)J$")>;
|
||||
def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone], (instregex "BRX(H|LE)$")>;
|
||||
|
||||
// Trap
|
||||
def : InstRW<[VBU], (instregex "(Cond)?Trap$")>;
|
||||
|
||||
// Compare and trap
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?C(G)?IT$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?C(G)?RT$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CLG(I|R)T$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CLFIT$")>;
|
||||
def : InstRW<[FXU], (instregex "(Asm.*)?CLRT$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Select instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Select pseudo
|
||||
def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
|
||||
|
||||
// CondStore pseudos
|
||||
def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Call instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[VBU, FXU, FXU, Lat3, GroupAlone], (instregex "BRAS$")>;
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BASR$")>;
|
||||
def : InstRW<[LSU, Lat4], (instregex "CallB(C)?R$")>;
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
|
||||
def : InstRW<[VBU], (instregex "CallBRCL$")>;
|
||||
def : InstRW<[VBU], (instregex "CallJG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Move instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Moves
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
|
||||
|
||||
// Move character
|
||||
def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
|
||||
|
||||
// Pseudo -> reg move
|
||||
def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
|
||||
def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
|
||||
def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
|
||||
def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
|
||||
def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
|
||||
|
||||
// Loads
|
||||
def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LG(RL)?$")>;
|
||||
def : InstRW<[LSU], (instregex "L128$")>;
|
||||
|
||||
def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
|
||||
def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
|
||||
|
||||
def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
|
||||
def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
|
||||
|
||||
// Load and test
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LT(G)?R$")>;
|
||||
|
||||
// Load on condition
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "(Asm.*)?LOC(G)?$")>;
|
||||
def : InstRW<[FXU, Lat2], (instregex "(Asm.*)?LOC(G)?R$")>;
|
||||
|
||||
// Stores
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
|
||||
|
||||
// Store on condition
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "(Asm.*)?STOC(G)?$")>;
|
||||
|
||||
// String moves.
|
||||
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Sign extensions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
|
||||
def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
|
||||
def : InstRW<[FXU], (instregex "LTGFR$")>;
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Zero extensions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LLG(C|H|F)R$")>;
|
||||
def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
|
||||
def : InstRW<[LSU], (instregex "LLHRL$")>;
|
||||
def : InstRW<[LSU], (instregex "LLG(C|H|F|HRL|FRL)$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Truncations
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Multi-register moves
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load multiple (estimated average of 5 ops)
|
||||
def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
|
||||
(instregex "LM(H|Y|G)?$")>;
|
||||
|
||||
// Store multiple (estimated average of 3 ops)
|
||||
def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
|
||||
(instregex "STM(H|Y|G)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Byte swaps
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Load address instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
|
||||
|
||||
// Load the Global Offset Table address
|
||||
def : InstRW<[FXU], (instregex "GOT$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Absolute and Negation
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
|
||||
def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
|
||||
def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
|
||||
def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
|
||||
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Insertion
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
|
||||
def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IILF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IILH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "IILL(64)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Addition
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "AH(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AIH$")>;
|
||||
def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AGFI$")>;
|
||||
def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AHI(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
|
||||
def : InstRW<[FXU], (instregex "ALGHSIK$")>;
|
||||
def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
|
||||
def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "ALR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "AR(K)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
|
||||
|
||||
// Logical addition with carry
|
||||
def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
|
||||
def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
|
||||
|
||||
// Add with sign extension (32 -> 64)
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "AGF$")>;
|
||||
def : InstRW<[FXU, Lat2], (instregex "AGFR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtraction
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "SH(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SLFI$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
|
||||
def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SLR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SR(K)?$")>;
|
||||
|
||||
// Subtraction with borrow
|
||||
def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
|
||||
def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
|
||||
|
||||
// Subtraction with sign extension (32 -> 64)
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "SGF$")>;
|
||||
def : InstRW<[FXU, Lat2], (instregex "SGFR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// AND
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NILF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NILH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NILL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "NR(K)?$")>;
|
||||
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// OR
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OGR(K)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
|
||||
def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OILF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OILH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OILL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "OR(K)?$")>;
|
||||
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// XOR
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "XIFMux$")>;
|
||||
def : InstRW<[FXU], (instregex "XGR(K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "XILF(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "XR(K)?$")>;
|
||||
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Multiplication
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
|
||||
def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
|
||||
def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
|
||||
def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
|
||||
def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
|
||||
def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
|
||||
def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
|
||||
def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Division and remainder
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FPU, FPU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
||||
(instregex "DSG(F)?R$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
|
||||
(instregex "DSG(F)?$")>;
|
||||
def : InstRW<[FPU, FPU, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
||||
(instregex "DL(G)?R$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
||||
(instregex "DL(G)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Shifts
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
|
||||
def : InstRW<[FXU], (instregex "SLA(K)?$")>;
|
||||
|
||||
// Rotate
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
|
||||
|
||||
// Rotate and insert
|
||||
def : InstRW<[FXU], (instregex "RISBG(N|32)?$")>;
|
||||
def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
|
||||
def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
|
||||
def : InstRW<[FXU], (instregex "RISBMux$")>;
|
||||
|
||||
// Rotate and Select
|
||||
def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Comparison
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CFI(Mux)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
|
||||
def : InstRW<[FXU], (instregex "C(G)?R$")>;
|
||||
def : InstRW<[FXU], (instregex "C(HI|IH)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
|
||||
def : InstRW<[FXU], (instregex "CLGR$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
|
||||
def : InstRW<[FXU], (instregex "CLIH$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CLR$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
|
||||
|
||||
// Compare halfword
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "CH(Y|RL)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "CGH(RL)?$")>;
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CHHSI$")>;
|
||||
|
||||
// Compare with sign extension (32 -> 64)
|
||||
def : InstRW<[FXU, LSU, Lat6], (instregex "CGF(RL)?$")>;
|
||||
def : InstRW<[FXU, Lat2], (instregex "CGFR$")>;
|
||||
|
||||
// Compare logical character
|
||||
def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "CLC$")>;
|
||||
|
||||
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
|
||||
|
||||
// Test under mask
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
|
||||
def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
|
||||
def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
|
||||
def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Prefetch
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[LSU], (instregex "PFD(RL)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Atomic operations
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
|
||||
|
||||
// Compare and swap
|
||||
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Transactional execution
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Transaction begin
|
||||
def : InstRW<[LSU, LSU, FXU, FXU, FXU, FXU, FXU, Lat15, GroupAlone],
|
||||
(instregex "TBEGIN(C|_nofloat)?$")>;
|
||||
|
||||
// Transaction end
|
||||
def : InstRW<[LSU, GroupAlone], (instregex "TEND$")>;
|
||||
|
||||
// Transaction abort
|
||||
def : InstRW<[LSU, GroupAlone], (instregex "TABORT$")>;
|
||||
|
||||
// Extract Transaction Nesting Depth
|
||||
def : InstRW<[FXU], (instregex "ETND$")>;
|
||||
|
||||
// Nontransactional store
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "NTSTG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Processor assist
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "PPA$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Miscellaneous Instructions.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Insert Program Mask
|
||||
def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
|
||||
|
||||
// Extract access register
|
||||
def : InstRW<[LSU], (instregex "EAR$")>;
|
||||
|
||||
// Find leftmost one
|
||||
def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
|
||||
|
||||
// Population count
|
||||
def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
|
||||
|
||||
// Extend
|
||||
def : InstRW<[FXU], (instregex "AEXT128_64$")>;
|
||||
def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
|
||||
|
||||
// String instructions
|
||||
def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
|
||||
|
||||
// Move with key
|
||||
def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
|
||||
|
||||
// Extract CPU Time
|
||||
def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
|
||||
|
||||
// Execute
|
||||
def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
|
||||
|
||||
// Program return
|
||||
def : InstRW<[FXU, Lat30], (instregex "PR$")>;
|
||||
|
||||
// Inline assembly
|
||||
def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "STCK(F)?$")>;
|
||||
def : InstRW<[LSU, LSU, LSU, LSU, FXU, FXU, Lat20, GroupAlone],
|
||||
(instregex "STCKE$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
|
||||
def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
|
||||
|
||||
// Store real address
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// .insn directive instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// An "empty" sched-class will be assigned instead of the "invalid sched-class".
|
||||
// getNumDecoderSlots() will then return 1 instead of 0.
|
||||
def : InstRW<[], (instregex "Insn.*")>;
|
||||
|
||||
|
||||
// ----------------------------- Floating point ----------------------------- //
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Select instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
|
||||
def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Move instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load zero
|
||||
def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
|
||||
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
|
||||
|
||||
// Load
|
||||
def : InstRW<[FXU], (instregex "LER$")>;
|
||||
def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
|
||||
def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
|
||||
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
|
||||
|
||||
// Load and Test
|
||||
def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
|
||||
def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
|
||||
def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat9, GroupAlone], (instregex "LTXBR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat9, GroupAlone],
|
||||
(instregex "LTXBRCompare(_VecPseudo)?$")>;
|
||||
|
||||
// Copy sign
|
||||
def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
|
||||
def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Load instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[LSU], (instregex "LE(Y)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
|
||||
def : InstRW<[LSU], (instregex "LX$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Store instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
|
||||
def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Conversion instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load rounded
|
||||
def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
|
||||
|
||||
// Load lengthened
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
|
||||
def : InstRW<[FPU], (instregex "LDEBR$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
|
||||
def : InstRW<[FPU, FPU, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
|
||||
|
||||
// Convert from fixed / logical
|
||||
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, FPU, Lat11, GroupAlone], (instregex "CX(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
|
||||
def : InstRW<[FXU, FPU, FPU, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
|
||||
|
||||
// Convert to fixed / logical
|
||||
def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR$")>;
|
||||
def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
|
||||
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
|
||||
def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Unary arithmetic
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Load Complement / Negative / Positive
|
||||
def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
|
||||
def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
|
||||
def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
|
||||
def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
|
||||
|
||||
// Square root
|
||||
def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
|
||||
def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "SQXBR$")>;
|
||||
|
||||
// Load FP integer
|
||||
def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
|
||||
def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
|
||||
def : InstRW<[FPU, FPU, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Binary arithmetic
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Addition
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
|
||||
def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat20, GroupAlone], (instregex "AXBR$")>;
|
||||
|
||||
// Subtraction
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
|
||||
def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat20, GroupAlone], (instregex "SXBR$")>;
|
||||
|
||||
// Multiply
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
|
||||
def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
|
||||
def : InstRW<[FPU, FPU, Lat10, GroupAlone], (instregex "MXDBR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "MXBR$")>;
|
||||
|
||||
// Multiply and add / subtract
|
||||
def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
|
||||
def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
|
||||
def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
|
||||
def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
|
||||
|
||||
// Division
|
||||
def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
|
||||
def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "DXBR$")>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FP: Comparisons
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Compare
|
||||
def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
|
||||
def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
|
||||
def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
|
||||
|
||||
// Test Data Class
|
||||
def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
|
||||
def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
|
||||
|
||||
}
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
#include "SystemZTargetMachine.h"
|
||||
#include "SystemZTargetTransformInfo.h"
|
||||
#include "SystemZMachineScheduler.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/CodeGen/TargetPassConfig.h"
|
||||
#include "llvm/Support/TargetRegistry.h"
|
||||
@ -17,7 +18,6 @@
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
extern cl::opt<bool> MISchedPostRA;
|
||||
extern "C" void LLVMInitializeSystemZTarget() {
|
||||
// Register the target.
|
||||
RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget());
|
||||
@ -114,6 +114,12 @@ public:
|
||||
return getTM<SystemZTargetMachine>();
|
||||
}
|
||||
|
||||
ScheduleDAGInstrs *
|
||||
createPostMachineScheduler(MachineSchedContext *C) const override {
|
||||
return new ScheduleDAGMI(C, make_unique<SystemZPostRASchedStrategy>(C),
|
||||
/*IsPostRA=*/true);
|
||||
}
|
||||
|
||||
void addIRPasses() override;
|
||||
bool addInstSelector() override;
|
||||
void addPreSched2() override;
|
||||
@ -180,12 +186,8 @@ void SystemZPassConfig::addPreEmitPass() {
|
||||
// Do final scheduling after all other optimizations, to get an
|
||||
// optimal input for the decoder (branch relaxation must happen
|
||||
// after block placement).
|
||||
if (getOptLevel() != CodeGenOpt::None) {
|
||||
if (MISchedPostRA)
|
||||
addPass(&PostMachineSchedulerID);
|
||||
else
|
||||
addPass(&PostRASchedulerID);
|
||||
}
|
||||
if (getOptLevel() != CodeGenOpt::None)
|
||||
addPass(&PostMachineSchedulerID);
|
||||
}
|
||||
|
||||
TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
|
||||
|
||||
@ -42,29 +42,29 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double>,
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
|
||||
; CHECK: vst [[VTMP]], 128(%r2)
|
||||
; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK-DAG: vst [[VTMP]], 128(%r2)
|
||||
; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
|
||||
; CHECK: vst [[VTMP]], 112(%r2)
|
||||
; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK-DAG: vst [[VTMP]], 112(%r2)
|
||||
; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
|
||||
; CHECK: vst [[VTMP]], 96(%r2)
|
||||
; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK-DAG: vst [[VTMP]], 96(%r2)
|
||||
; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
|
||||
; CHECK: vst [[VTMP]], 80(%r2)
|
||||
; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK-DAG: vst [[VTMP]], 80(%r2)
|
||||
; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
|
||||
; CHECK: vst [[VTMP]], 64(%r2)
|
||||
; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK-DAG: vst [[VTMP]], 64(%r2)
|
||||
; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
|
||||
; CHECK: vst [[VTMP]], 48(%r2)
|
||||
; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK-DAG: vst [[VTMP]], 48(%r2)
|
||||
; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
|
||||
; CHECK: vst [[VTMP]], 32(%r2)
|
||||
; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK-DAG: vst [[VTMP]], 32(%r2)
|
||||
; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
|
||||
; CHECK: vst [[VTMP]], 16(%r2)
|
||||
; CHECK: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK-DAG: vst [[VTMP]], 16(%r2)
|
||||
; CHECK-DAG: larl [[TMP:%r[0-5]]], .LCPI
|
||||
; CHECK: vl [[VTMP:%v[0-9]+]], 0([[TMP]])
|
||||
; CHECK: vst [[VTMP]], 0(%r2)
|
||||
; CHECK: br %r14
|
||||
|
||||
@ -7,9 +7,9 @@
|
||||
|
||||
define <4 x i32> @f1(<4 x i32> %x, i64 %y) {
|
||||
; CHECK-CODE-LABEL: f1:
|
||||
; CHECK-CODE: vlvgf [[ELT:%v[0-9]+]], %r2, 0
|
||||
; CHECK-CODE: larl [[REG:%r[0-5]]],
|
||||
; CHECK-CODE: vl [[MASK:%v[0-9]+]], 0([[REG]])
|
||||
; CHECK-CODE-DAG: vlvgf [[ELT:%v[0-9]+]], %r2, 0
|
||||
; CHECK-CODE-DAG: larl [[REG:%r[0-5]]],
|
||||
; CHECK-CODE-DAG: vl [[MASK:%v[0-9]+]], 0([[REG]])
|
||||
; CHECK-CODE: vperm %v24, %v24, [[ELT]], [[MASK]]
|
||||
; CHECK-CODE: br %r14
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user