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[NFC][Test] Add the vavg test for PowerPC
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QingShan Zhang
parent
2090af3d5e
commit
f910762b1b
189
test/CodeGen/PowerPC/vavg.ll
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189
test/CodeGen/PowerPC/vavg.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-P7 %s
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define <8 x i16> @test_v8i16(<8 x i16> %m, <8 x i16> %n) {
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; CHECK-P9-LABEL: test_v8i16:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: xxlnor 34, 34, 34
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; CHECK-P9-NEXT: vspltish 4, 1
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; CHECK-P9-NEXT: vsubuhm 2, 3, 2
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; CHECK-P9-NEXT: vsrh 2, 2, 4
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: test_v8i16:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: xxlnor 34, 34, 34
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; CHECK-P8-NEXT: vspltish 4, 1
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; CHECK-P8-NEXT: vsubuhm 2, 3, 2
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; CHECK-P8-NEXT: vsrh 2, 2, 4
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; CHECK-P8-NEXT: blr
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;
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; CHECK-P7-LABEL: test_v8i16:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: xxlnor 34, 34, 34
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; CHECK-P7-NEXT: vspltish 4, 1
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; CHECK-P7-NEXT: vsubuhm 2, 3, 2
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; CHECK-P7-NEXT: vsrh 2, 2, 4
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; CHECK-P7-NEXT: blr
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entry:
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%add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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%add1 = add <8 x i16> %add, %n
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%shr = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <8 x i16> %shr
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}
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define <8 x i16> @test_v8i16_sign(<8 x i16> %m, <8 x i16> %n) {
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; CHECK-P9-LABEL: test_v8i16_sign:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: xxlnor 34, 34, 34
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; CHECK-P9-NEXT: vspltish 4, 1
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; CHECK-P9-NEXT: vsubuhm 2, 3, 2
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; CHECK-P9-NEXT: vsrah 2, 2, 4
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: test_v8i16_sign:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: xxlnor 34, 34, 34
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; CHECK-P8-NEXT: vspltish 4, 1
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; CHECK-P8-NEXT: vsubuhm 2, 3, 2
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; CHECK-P8-NEXT: vsrah 2, 2, 4
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; CHECK-P8-NEXT: blr
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;
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; CHECK-P7-LABEL: test_v8i16_sign:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: xxlnor 34, 34, 34
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; CHECK-P7-NEXT: vspltish 4, 1
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; CHECK-P7-NEXT: vsubuhm 2, 3, 2
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; CHECK-P7-NEXT: vsrah 2, 2, 4
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; CHECK-P7-NEXT: blr
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entry:
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%add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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%add1 = add <8 x i16> %add, %n
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%shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <8 x i16> %shr
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}
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define <4 x i32> @test_v4i32(<4 x i32> %m, <4 x i32> %n) {
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; CHECK-P9-LABEL: test_v4i32:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: xxlnor 34, 34, 34
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; CHECK-P9-NEXT: vspltisw 4, 1
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; CHECK-P9-NEXT: vsubuwm 2, 3, 2
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; CHECK-P9-NEXT: vsrw 2, 2, 4
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: test_v4i32:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: xxlnor 34, 34, 34
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; CHECK-P8-NEXT: vspltisw 4, 1
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; CHECK-P8-NEXT: vsubuwm 2, 3, 2
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; CHECK-P8-NEXT: vsrw 2, 2, 4
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; CHECK-P8-NEXT: blr
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;
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; CHECK-P7-LABEL: test_v4i32:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: xxlnor 34, 34, 34
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; CHECK-P7-NEXT: vspltisw 4, 1
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; CHECK-P7-NEXT: vsubuwm 2, 3, 2
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; CHECK-P7-NEXT: vsrw 2, 2, 4
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; CHECK-P7-NEXT: blr
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entry:
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%add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>
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%add1 = add <4 x i32> %add, %n
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%shr = lshr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %shr
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}
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define <4 x i32> @test_v4i32_sign(<4 x i32> %m, <4 x i32> %n) {
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; CHECK-P9-LABEL: test_v4i32_sign:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: xxlnor 34, 34, 34
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; CHECK-P9-NEXT: vspltisw 4, 1
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; CHECK-P9-NEXT: vsubuwm 2, 3, 2
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; CHECK-P9-NEXT: vsraw 2, 2, 4
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: test_v4i32_sign:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: xxlnor 34, 34, 34
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; CHECK-P8-NEXT: vspltisw 4, 1
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; CHECK-P8-NEXT: vsubuwm 2, 3, 2
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; CHECK-P8-NEXT: vsraw 2, 2, 4
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; CHECK-P8-NEXT: blr
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;
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; CHECK-P7-LABEL: test_v4i32_sign:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: xxlnor 34, 34, 34
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; CHECK-P7-NEXT: vspltisw 4, 1
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; CHECK-P7-NEXT: vsubuwm 2, 3, 2
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; CHECK-P7-NEXT: vsraw 2, 2, 4
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; CHECK-P7-NEXT: blr
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entry:
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%add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>
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%add1 = add <4 x i32> %add, %n
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%shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %shr
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}
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define <16 x i8> @test_v16i8(<16 x i8> %m, <16 x i8> %n) {
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; CHECK-P9-LABEL: test_v16i8:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: xxlnor 34, 34, 34
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; CHECK-P9-NEXT: xxspltib 36, 1
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; CHECK-P9-NEXT: vsububm 2, 3, 2
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; CHECK-P9-NEXT: vsrb 2, 2, 4
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: test_v16i8:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: xxlnor 34, 34, 34
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; CHECK-P8-NEXT: vspltisb 4, 1
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; CHECK-P8-NEXT: vsububm 2, 3, 2
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; CHECK-P8-NEXT: vsrb 2, 2, 4
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; CHECK-P8-NEXT: blr
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;
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; CHECK-P7-LABEL: test_v16i8:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: xxlnor 34, 34, 34
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; CHECK-P7-NEXT: vspltisb 4, 1
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; CHECK-P7-NEXT: vsububm 2, 3, 2
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; CHECK-P7-NEXT: vsrb 2, 2, 4
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; CHECK-P7-NEXT: blr
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entry:
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%add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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%add1 = add <16 x i8> %add, %n
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%shr = lshr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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ret <16 x i8> %shr
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}
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define <16 x i8> @test_v16i8_sign(<16 x i8> %m, <16 x i8> %n) {
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; CHECK-P9-LABEL: test_v16i8_sign:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: xxlnor 34, 34, 34
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; CHECK-P9-NEXT: xxspltib 36, 1
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; CHECK-P9-NEXT: vsububm 2, 3, 2
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; CHECK-P9-NEXT: vsrab 2, 2, 4
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: test_v16i8_sign:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: xxlnor 34, 34, 34
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; CHECK-P8-NEXT: vspltisb 4, 1
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; CHECK-P8-NEXT: vsububm 2, 3, 2
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; CHECK-P8-NEXT: vsrab 2, 2, 4
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; CHECK-P8-NEXT: blr
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;
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; CHECK-P7-LABEL: test_v16i8_sign:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: xxlnor 34, 34, 34
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; CHECK-P7-NEXT: vspltisb 4, 1
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; CHECK-P7-NEXT: vsububm 2, 3, 2
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; CHECK-P7-NEXT: vsrab 2, 2, 4
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; CHECK-P7-NEXT: blr
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entry:
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%add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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%add1 = add <16 x i8> %add, %n
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%shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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ret <16 x i8> %shr
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}
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