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Fix ARM assembly parsing for upper case condition codes on IT instructions.

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llvm-svn: 155720
This commit is contained in:
Richard Barton 2012-04-27 17:34:01 +00:00
parent 82bc1975d7
commit f9237b25e6
2 changed files with 14 additions and 1 deletions
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2
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -2674,7 +2674,7 @@ parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
const AsmToken &Tok = Parser.getTok();
if (!Tok.is(AsmToken::Identifier))
return MatchOperand_NoMatch;
unsigned CC = StringSwitch<unsigned>(Tok.getString())
unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)
.Case("hs", ARMCC::HS)

13
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -509,6 +509,19 @@ _func:
@ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b]
@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
@ Should also work for UPPER CASE condition codes.
ITEET EQ
ADDEQ R0, R1, R2
NOPNE
SUBNE R5, R6, R7
ADDEQ R1, R2, #4
@ CHECK: iteet eq @ encoding: [0x0d,0xbf]
@ CHECK: addeq r0, r1, r2 @ encoding: [0x88,0x18]
@ CHECK: nopne @ encoding: [0x00,0xbf]
@ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b]
@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
@------------------------------------------------------------------------------
@ LDC{L}/LDC2{L}