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[AMDGPU][MC] Added tests for checking error position
See bug 47519: https://bugs.llvm.org/show_bug.cgi?id=47519 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D90925
This commit is contained in:
Dmitry Preobrazhensky
parent
6a6e7afc31
commit
f9396b47fe
1044
test/MC/AMDGPU/gfx10_err_pos.s
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1044
test/MC/AMDGPU/gfx10_err_pos.s
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25
test/MC/AMDGPU/gfx7_err_pos.s
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25
test/MC/AMDGPU/gfx7_err_pos.s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
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//==============================================================================
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// d16 modifier is not supported on this GPU
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image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
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// CHECK: error: d16 modifier is not supported on this GPU
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// CHECK-NEXT:{{^}}image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
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// CHECK-NEXT:{{^}}^
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//==============================================================================
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// integer clamping is not supported on this GPU
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v_add_co_u32 v84, s[4:5], v13, v31 clamp
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// CHECK: error: integer clamping is not supported on this GPU
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// CHECK-NEXT:{{^}}v_add_co_u32 v84, s[4:5], v13, v31 clamp
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// CHECK-NEXT:{{^}}^
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//==============================================================================
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// invalid literal operand
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v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
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// CHECK: error: invalid literal operand
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// CHECK-NEXT:{{^}}v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
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// CHECK-NEXT:{{^}}^
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38
test/MC/AMDGPU/gfx8_err_pos.s
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38
test/MC/AMDGPU/gfx8_err_pos.s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
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//==============================================================================
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// a16 modifier is not supported on this GPU
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image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 a16
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// CHECK: error: a16 modifier is not supported on this GPU
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// CHECK-NEXT:{{^}}image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 a16
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// expected a 20-bit unsigned offset
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s_atc_probe 0x7, s[4:5], -1
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// CHECK: error: expected a 20-bit unsigned offset
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// CHECK-NEXT:{{^}}s_atc_probe 0x7, s[4:5], -1
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// CHECK-NEXT:{{^}} ^
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s_store_dword s1, s[2:3], 0xFFFFFFFFFFF00000
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// CHECK: error: expected a 20-bit unsigned offset
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// CHECK-NEXT:{{^}}s_store_dword s1, s[2:3], 0xFFFFFFFFFFF00000
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// flat offset modifier is not supported on this GPU
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flat_atomic_add v[3:4], v5 inst_offset:8 slc
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// CHECK: error: flat offset modifier is not supported on this GPU
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// CHECK-NEXT:{{^}}flat_atomic_add v[3:4], v5 inst_offset:8 slc
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// image data size does not match dmask and tfe
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image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
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// CHECK: error: image data size does not match dmask and tfe
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// CHECK-NEXT:{{^}}image_gather4 v[5:6], v1, s[8:15], s[12:15] dmask:0x1 d16
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// CHECK-NEXT:{{^}}^
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33
test/MC/AMDGPU/gfx908_err_pos.s
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test/MC/AMDGPU/gfx908_err_pos.s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
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//==============================================================================
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// invalid neg_hi value
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v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[0,2]
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// CHECK: error: invalid neg_hi value
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// CHECK-NEXT:{{^}}v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[0,2]
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// invalid neg_lo value
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v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[2,0]
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// CHECK: error: invalid neg_lo value
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// CHECK-NEXT:{{^}}v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[2,0]
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// invalid op_sel_hi value
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v_dot2_f32_f16 v0, v1, v2, v3 op_sel_hi:[2,0]
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// CHECK: error: invalid op_sel_hi value
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// CHECK-NEXT:{{^}}v_dot2_f32_f16 v0, v1, v2, v3 op_sel_hi:[2,0]
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// source operand must be either a VGPR or an inline constant
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v_accvgpr_write a2, execz
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// CHECK: error: source operand must be either a VGPR or an inline constant
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// CHECK-NEXT:{{^}}v_accvgpr_write a2, execz
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// CHECK-NEXT:{{^}} ^
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157
test/MC/AMDGPU/gfx9_err_pos.s
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157
test/MC/AMDGPU/gfx9_err_pos.s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
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//==============================================================================
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// 'null' operand is not supported on this GPU
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s_add_u32 null, null, null
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// CHECK: error: 'null' operand is not supported on this GPU
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// CHECK-NEXT:{{^}}s_add_u32 null, null, null
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// duplicate VGPR index mode
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s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC1,DST)
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// CHECK: error: duplicate VGPR index mode
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// CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC1,DST)
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// expected a 12-bit unsigned offset
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flat_load_dword v1, v[3:4] offset:-1
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// CHECK: error: expected a 12-bit unsigned offset
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// CHECK-NEXT:{{^}}flat_load_dword v1, v[3:4] offset:-1
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// CHECK-NEXT:{{^}} ^
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flat_load_dword v1, v[3:4] offset:4096
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// CHECK: error: expected a 12-bit unsigned offset
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// CHECK-NEXT:{{^}}flat_load_dword v1, v[3:4] offset:4096
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// expected a 13-bit signed offset
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global_load_dword v1, v[3:4] off, offset:-4097
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// CHECK: error: expected a 13-bit signed offset
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// CHECK-NEXT:{{^}}global_load_dword v1, v[3:4] off, offset:-4097
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// expected a VGPR index mode
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s_set_gpr_idx_on s0, gpr_idx(SRC0,
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// CHECK: error: expected a VGPR index mode
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// CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, gpr_idx(SRC0,
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// expected a VGPR index mode or a closing parenthesis
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s_set_gpr_idx_on s0, gpr_idx(
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// CHECK: error: expected a VGPR index mode or a closing parenthesis
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// CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, gpr_idx(
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// CHECK-NEXT:{{^}} ^
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s_set_gpr_idx_on s0, gpr_idx(X)
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// CHECK: error: expected a VGPR index mode or a closing parenthesis
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// CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, gpr_idx(X)
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// expected a comma or a closing parenthesis
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s_set_gpr_idx_on s0, gpr_idx(DST
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// CHECK: error: expected a comma or a closing parenthesis
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// CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, gpr_idx(DST
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// expected absolute expression
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s_set_gpr_idx_on s0, gpr_idx
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// CHECK: error: expected absolute expression
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// CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, gpr_idx
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// CHECK-NEXT:{{^}} ^
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s_set_gpr_idx_on s0, s1
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// CHECK: error: expected absolute expression
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// CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, s1
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// invalid atomic image dmask
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image_atomic_add v252, v2, s[8:15]
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// CHECK: error: invalid atomic image dmask
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// CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15]
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// CHECK-NEXT:{{^}}^
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image_atomic_cmpswap v[4:7], v[192:195], s[28:35] dmask:0xe tfe
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// CHECK: error: invalid atomic image dmask
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// CHECK-NEXT:{{^}}image_atomic_cmpswap v[4:7], v[192:195], s[28:35] dmask:0xe tfe
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// CHECK-NEXT:{{^}}^
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//==============================================================================
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// invalid image_gather dmask: only one bit must be set
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image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3
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// CHECK: error: invalid image_gather dmask: only one bit must be set
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// CHECK-NEXT:{{^}}image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3
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// CHECK-NEXT:{{^}}^
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//==============================================================================
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// invalid immediate: only 4-bit values are legal
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s_set_gpr_idx_on s0, 16
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// CHECK: error: invalid immediate: only 4-bit values are legal
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// CHECK-NEXT:{{^}}s_set_gpr_idx_on s0, 16
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// invalid operand (violates constant bus restrictions)
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v_add_f32_e64 v0, flat_scratch_hi, m0
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// CHECK: error: invalid operand (violates constant bus restrictions)
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// CHECK-NEXT:{{^}}v_add_f32_e64 v0, flat_scratch_hi, m0
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// CHECK-NEXT:{{^}}^
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//==============================================================================
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// r128 modifier is not supported on this GPU
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image_atomic_add v10, v6, s[8:15] dmask:0x1 r128
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// CHECK: error: r128 modifier is not supported on this GPU
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// CHECK-NEXT:{{^}}image_atomic_add v10, v6, s[8:15] dmask:0x1 r128
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// unified format is not supported on this GPU
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tbuffer_store_format_xyzw v[1:4], v1, s[4:7], s0 format:[BUF_FMT_8_SNORM,BUF_DATA_FORMAT_8] idxen
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// CHECK: error: unified format is not supported on this GPU
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// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], v1, s[4:7], s0 format:[BUF_FMT_8_SNORM,BUF_DATA_FORMAT_8] idxen
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// duplicate format
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tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], dfmt:1 s0 format:[BUF_NUM_FORMAT_FLOAT]
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// CHECK: error: duplicate format
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// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], dfmt:1 s0 format:[BUF_NUM_FORMAT_FLOAT]
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// out of range dfmt
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tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:16 nfmt:1 s0
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// CHECK: error: out of range dfmt
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// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:16 nfmt:1 s0
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// CHECK-NEXT:{{^}} ^
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//==============================================================================
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// out of range nfmt
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tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:1 nfmt:-1 s0
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// CHECK: error: out of range nfmt
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// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] dfmt:1 nfmt:-1 s0
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// CHECK-NEXT:{{^}} ^
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