From f9498d7f4a46016046a04219745f6a162073d6fa Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Thu, 24 Jun 2021 18:03:06 -0500 Subject: [PATCH] [PowerPC] Fix bswap combine for big endian systems Commit 0464586ac515e8cfebe4c7615387fd625c8869f5 added a combine for a 64-bit load feeding a bswap but the implementation is only correct for little endian systems. This fixes it for big endian systems. --- lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++++- test/CodeGen/PowerPC/bswap-load-store.ll | 9 +++++---- test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll | 10 +++++----- 3 files changed, 15 insertions(+), 10 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 5cb4470e042..f2bc01bc6d9 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -15262,7 +15262,11 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, SDValue Hi = DAG.getLoad(MVT::i32, dl, LD->getChain(), BasePtr, LD->getPointerInfo(), LD->getAlignment()); Hi = DAG.getNode(ISD::BSWAP, dl, MVT::i32, Hi); - SDValue Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Hi, Lo); + SDValue Res; + if (Subtarget.isLittleEndian()) + Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Hi, Lo); + else + Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Hi.getOperand(0).getValue(1), Lo.getOperand(0).getValue(1)); diff --git a/test/CodeGen/PowerPC/bswap-load-store.ll b/test/CodeGen/PowerPC/bswap-load-store.ll index e21f810040d..0c9b7a70945 100644 --- a/test/CodeGen/PowerPC/bswap-load-store.ll +++ b/test/CodeGen/PowerPC/bswap-load-store.ll @@ -151,11 +151,12 @@ define i64 @LDBRX(i8* %ptr, i64 %off) { ; ; X64-LABEL: LDBRX: ; X64: # %bb.0: -; X64-NEXT: li r5, 4 -; X64-NEXT: lwbrx r6, r3, r4 +; X64-NEXT: li r6, 4 +; X64-NEXT: lwbrx r5, r3, r4 ; X64-NEXT: add r3, r3, r4 -; X64-NEXT: lwbrx r3, r3, r5 -; X64-NEXT: rldimi r3, r6, 32, 0 +; X64-NEXT: lwbrx r3, r3, r6 +; X64-NEXT: rldimi r5, r3, 32, 0 +; X64-NEXT: mr r3, r5 ; X64-NEXT: blr ; ; PWR7_64-LABEL: LDBRX: diff --git a/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll b/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll index 27e7c7b73af..d8889cd7c79 100644 --- a/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll +++ b/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll @@ -7,8 +7,8 @@ define void @bs(i64* %p) { ; CHECK-NEXT: li 4, 4 ; CHECK-NEXT: lwbrx 5, 0, 3 ; CHECK-NEXT: lwbrx 4, 3, 4 -; CHECK-NEXT: rldimi 4, 5, 32, 0 -; CHECK-NEXT: std 4, 0(3) +; CHECK-NEXT: rldimi 5, 4, 32, 0 +; CHECK-NEXT: std 5, 0(3) ; CHECK-NEXT: blr %x = load i64, i64* %p, align 8 %b = call i64 @llvm.bswap.i64(i64 %x) @@ -42,9 +42,9 @@ define i64 @misaligned_ld(i64* %p) { ; CHECK-LABEL: misaligned_ld: ; CHECK: # %bb.0: ; CHECK-NEXT: li 4, 4 -; CHECK-NEXT: lwbrx 5, 0, 3 -; CHECK-NEXT: lwbrx 3, 3, 4 -; CHECK-NEXT: rldimi 3, 5, 32, 0 +; CHECK-NEXT: lwbrx 4, 3, 4 +; CHECK-NEXT: lwbrx 3, 0, 3 +; CHECK-NEXT: rldimi 3, 4, 32, 0 ; CHECK-NEXT: blr %x = load i64, i64* %p, align 1 %b = call i64 @llvm.bswap.i64(i64 %x)