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Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so

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that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.

llvm-svn: 107487
This commit is contained in:
Bob Wilson 2010-07-02 17:23:44 +00:00
parent 7c64164e6a
commit f96aab3079
3 changed files with 24 additions and 38 deletions
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4
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -1044,8 +1044,8 @@ void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
Val = Imm8 << (8 * ByteNum);
} else if ((OpCmode & 0xe) == 0xc) {
// 32-bit vector elements, one byte with low bits set
unsigned ByteNum = (OpCmode & 0x1);
Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (1 - ByteNum)));
unsigned ByteNum = 1 + (OpCmode & 0x1);
Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
} else if (OpCmode == 0x1e) {
// 64-bit vector elements
for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {

4
lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
View File

@ -799,8 +799,8 @@ void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
Val = Imm8 << (8 * ByteNum);
} else if ((OpCmode & 0xe) == 0xc) {
// 32-bit vector elements, one byte with low bits set
unsigned ByteNum = (OpCmode & 0x1);
Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (1 - ByteNum)));
unsigned ByteNum = 1 + (OpCmode & 0x1);
Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
} else if (OpCmode == 0x1e) {
// 64-bit vector elements
for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {

54
test/CodeGen/ARM/vmov.ll
View File

@ -2,135 +2,121 @@
define <8 x i8> @v_movi8() nounwind {
;CHECK: v_movi8:
;CHECK: vmov.i8
;CHECK: vmov.i8 d0, #0x8
ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <4 x i16> @v_movi16a() nounwind {
;CHECK: v_movi16a:
;CHECK: vmov.i16
;CHECK: vmov.i16 d0, #0x10
ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
}
; 0x1000 = 4096
define <4 x i16> @v_movi16b() nounwind {
;CHECK: v_movi16b:
;CHECK: vmov.i16
;CHECK: vmov.i16 d0, #0x1000
ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
}
define <2 x i32> @v_movi32a() nounwind {
;CHECK: v_movi32a:
;CHECK: vmov.i32
;CHECK: vmov.i32 d0, #0x20
ret <2 x i32> < i32 32, i32 32 >
}
; 0x2000 = 8192
define <2 x i32> @v_movi32b() nounwind {
;CHECK: v_movi32b:
;CHECK: vmov.i32
;CHECK: vmov.i32 d0, #0x2000
ret <2 x i32> < i32 8192, i32 8192 >
}
; 0x200000 = 2097152
define <2 x i32> @v_movi32c() nounwind {
;CHECK: v_movi32c:
;CHECK: vmov.i32
;CHECK: vmov.i32 d0, #0x200000
ret <2 x i32> < i32 2097152, i32 2097152 >
}
; 0x20000000 = 536870912
define <2 x i32> @v_movi32d() nounwind {
;CHECK: v_movi32d:
;CHECK: vmov.i32
;CHECK: vmov.i32 d0, #0x20000000
ret <2 x i32> < i32 536870912, i32 536870912 >
}
; 0x20ff = 8447
define <2 x i32> @v_movi32e() nounwind {
;CHECK: v_movi32e:
;CHECK: vmov.i32
;CHECK: vmov.i32 d0, #0x20FF
ret <2 x i32> < i32 8447, i32 8447 >
}
; 0x20ffff = 2162687
define <2 x i32> @v_movi32f() nounwind {
;CHECK: v_movi32f:
;CHECK: vmov.i32
;CHECK: vmov.i32 d0, #0x20FFFF
ret <2 x i32> < i32 2162687, i32 2162687 >
}
; 0xff0000ff0000ffff = 18374687574888349695
define <1 x i64> @v_movi64() nounwind {
;CHECK: v_movi64:
;CHECK: vmov.i64
;CHECK: vmov.i64 d0, #0xFF0000FF0000FFFF
ret <1 x i64> < i64 18374687574888349695 >
}
define <16 x i8> @v_movQi8() nounwind {
;CHECK: v_movQi8:
;CHECK: vmov.i8
;CHECK: vmov.i8 q0, #0x8
ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <8 x i16> @v_movQi16a() nounwind {
;CHECK: v_movQi16a:
;CHECK: vmov.i16
;CHECK: vmov.i16 q0, #0x10
ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
}
; 0x1000 = 4096
define <8 x i16> @v_movQi16b() nounwind {
;CHECK: v_movQi16b:
;CHECK: vmov.i16
;CHECK: vmov.i16 q0, #0x1000
ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
}
define <4 x i32> @v_movQi32a() nounwind {
;CHECK: v_movQi32a:
;CHECK: vmov.i32
;CHECK: vmov.i32 q0, #0x20
ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
}
; 0x2000 = 8192
define <4 x i32> @v_movQi32b() nounwind {
;CHECK: v_movQi32b:
;CHECK: vmov.i32
;CHECK: vmov.i32 q0, #0x2000
ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
}
; 0x200000 = 2097152
define <4 x i32> @v_movQi32c() nounwind {
;CHECK: v_movQi32c:
;CHECK: vmov.i32
;CHECK: vmov.i32 q0, #0x200000
ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
}
; 0x20000000 = 536870912
define <4 x i32> @v_movQi32d() nounwind {
;CHECK: v_movQi32d:
;CHECK: vmov.i32
;CHECK: vmov.i32 q0, #0x20000000
ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
}
; 0x20ff = 8447
define <4 x i32> @v_movQi32e() nounwind {
;CHECK: v_movQi32e:
;CHECK: vmov.i32
;CHECK: vmov.i32 q0, #0x20FF
ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
}
; 0x20ffff = 2162687
define <4 x i32> @v_movQi32f() nounwind {
;CHECK: v_movQi32f:
;CHECK: vmov.i32
;CHECK: vmov.i32 q0, #0x20FFFF
ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
}
; 0xff0000ff0000ffff = 18374687574888349695
define <2 x i64> @v_movQi64() nounwind {
;CHECK: v_movQi64:
;CHECK: vmov.i64
;CHECK: vmov.i64 q0, #0xFF0000FF0000FFFF
ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
}