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[mips] Stop caching the result of hasMips64(), isABI_O32(), isABI_N32(), and isABI_N64() from MipsSubTarget in MipsTargetLowering
Summary: The short name is quite convenient so provide an accessor for them instead. No functional change Depends on D3177 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3178 llvm-svn: 204911
This commit is contained in:
Daniel Sanders
parent
179b6d46c2
commit
f96fa11e3f
@ -202,12 +202,9 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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}
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}
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MipsTargetLowering::
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MipsTargetLowering(MipsTargetMachine &TM)
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: TargetLowering(TM, new MipsTargetObjectFile()),
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Subtarget(&TM.getSubtarget<MipsSubtarget>()),
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HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
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IsO32(Subtarget->isABI_O32()) {
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MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
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: TargetLowering(TM, new MipsTargetObjectFile()),
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Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
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// Mips does not have i1 type, so use i32 for
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// setcc operations results (slt, sgt, ...).
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setBooleanContents(ZeroOrOneBooleanContent);
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@ -253,7 +250,7 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::FABS, MVT::f64, Custom);
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}
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if (HasMips64) {
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if (hasMips64()) {
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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@ -265,14 +262,14 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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}
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if (!HasMips64) {
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if (!hasMips64()) {
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
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}
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setOperationAction(ISD::ADD, MVT::i32, Custom);
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if (HasMips64)
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if (hasMips64())
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setOperationAction(ISD::ADD, MVT::i64, Custom);
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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@ -374,7 +371,7 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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}
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if (HasMips64) {
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if (hasMips64()) {
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setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
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setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
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@ -390,12 +387,12 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::ADD);
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setMinFunctionAlignment(HasMips64 ? 3 : 2);
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setMinFunctionAlignment(hasMips64() ? 3 : 2);
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setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
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setStackPointerRegisterToSaveRestore(isN64() ? Mips::SP_64 : Mips::SP);
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setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
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setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
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setExceptionPointerRegister(isN64() ? Mips::A0_64 : Mips::A0);
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setExceptionSelectorRegister(isN64() ? Mips::A1_64 : Mips::A1);
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MaxStoresPerMemcpy = 16;
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@ -1419,7 +1416,7 @@ SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
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0);
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Chain = Addr.getValue(1);
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if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) {
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if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || isN64()) {
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// For PIC, the sequence is:
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// BRIND(load(Jumptable + index) + RelocBase)
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// RelocBase can be JumpTable, GOT or some sort of global base.
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@ -1500,7 +1497,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
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GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
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const GlobalValue *GV = N->getGlobal();
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64()) {
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const MipsTargetObjectFile &TLOF =
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(const MipsTargetObjectFile&)getObjFileLowering();
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@ -1519,7 +1516,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
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}
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if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
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return getAddrLocal(N, Ty, DAG, isN32() || IsN64);
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return getAddrLocal(N, Ty, DAG, isN32() || isN64());
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if (LargeGOT)
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return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16,
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@ -1527,7 +1524,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
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MachinePointerInfo::getGOT());
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return getAddrGlobal(N, Ty, DAG,
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HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16,
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hasMips64() ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16,
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DAG.getEntryNode(), MachinePointerInfo::getGOT());
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}
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@ -1536,10 +1533,10 @@ SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
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BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
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EVT Ty = Op.getValueType();
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64())
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return getAddrNonPIC(N, Ty, DAG);
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return getAddrLocal(N, Ty, DAG, isN32() || IsN64);
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return getAddrLocal(N, Ty, DAG, isN32() || isN64());
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}
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SDValue MipsTargetLowering::
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@ -1629,10 +1626,10 @@ lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
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JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
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EVT Ty = Op.getValueType();
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64())
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return getAddrNonPIC(N, Ty, DAG);
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return getAddrLocal(N, Ty, DAG, isN32() || IsN64);
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return getAddrLocal(N, Ty, DAG, isN32() || isN64());
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}
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SDValue MipsTargetLowering::
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@ -1650,10 +1647,10 @@ lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
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ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
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EVT Ty = Op.getValueType();
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64())
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return getAddrNonPIC(N, Ty, DAG);
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return getAddrLocal(N, Ty, DAG, isN32() || IsN64);
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return getAddrLocal(N, Ty, DAG, isN32() || isN64());
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}
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SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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@ -1844,7 +1841,7 @@ lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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SDLoc DL(Op);
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SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
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IsN64 ? Mips::FP_64 : Mips::FP, VT);
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isN64() ? Mips::FP_64 : Mips::FP, VT);
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return FrameAddr;
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}
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@ -1860,7 +1857,7 @@ SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MVT VT = Op.getSimpleValueType();
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unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
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unsigned RA = isN64() ? Mips::RA_64 : Mips::RA;
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MFI->setReturnAddressIsTaken(true);
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// Return RA, which contains the return address. Mark it an implicit live-in.
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@ -1882,12 +1879,12 @@ SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
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SDValue Offset = Op.getOperand(1);
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SDValue Handler = Op.getOperand(2);
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SDLoc DL(Op);
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EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
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EVT Ty = isN64() ? MVT::i64 : MVT::i32;
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// Store stack offset in V1, store jump target in V0. Glue CopyToReg and
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// EH_RETURN nodes, so that instructions are emitted back-to-back.
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unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
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unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
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unsigned OffsetReg = isN64() ? Mips::V1_64 : Mips::V1;
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unsigned AddrReg = isN64() ? Mips::V0_64 : Mips::V0;
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Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
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Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
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return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
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@ -2311,8 +2308,8 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
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// in PIC mode) allow symbols to be resolved via lazy binding.
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// The lazy binding stub requires GP to point to the GOT.
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if (IsPICCall && !InternalLinkage) {
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unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
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EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
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unsigned GPReg = isN64() ? Mips::GP_64 : Mips::GP;
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EVT Ty = isN64() ? MVT::i64 : MVT::i32;
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RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
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}
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@ -2381,7 +2378,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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getTargetMachine(), ArgLocs, *DAG.getContext());
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MipsCC::SpecialCallingConvType SpecialCallingConv =
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getSpecialCallingConv(Callee);
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MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo,
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MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo,
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SpecialCallingConv);
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MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
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@ -2410,9 +2407,8 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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if (!IsTailCall)
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Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
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SDValue StackPtr = DAG.getCopyFromReg(Chain, DL,
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IsN64 ? Mips::SP_64 : Mips::SP,
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getPointerTy());
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SDValue StackPtr = DAG.getCopyFromReg(
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Chain, DL, isN64() ? Mips::SP_64 : Mips::SP, getPointerTy());
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// With EABI is it possible to have 16 args on registers.
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std::deque< std::pair<unsigned, SDValue> > RegsToPass;
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@ -2499,7 +2495,8 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
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// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
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// node so that legalize doesn't hack it.
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bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
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bool IsPICCall = (isN64() || IsPIC); // true if calls are translated to
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// jalr $25
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bool GlobalOrExternal = false, InternalLinkage = false;
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SDValue CalleeLo;
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EVT Ty = Callee.getValueType();
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@ -2510,7 +2507,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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InternalLinkage = Val->hasInternalLinkage();
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if (InternalLinkage)
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Callee = getAddrLocal(G, Ty, DAG, isN32() || IsN64);
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Callee = getAddrLocal(G, Ty, DAG, isN32() || isN64());
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else if (LargeGOT)
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Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16,
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MipsII::MO_CALL_LO16, Chain,
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@ -2526,7 +2523,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
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const char *Sym = S->getSymbol();
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if (!IsN64 && !IsPIC) // !N64 && static
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if (!isN64() && !IsPIC) // !N64 && static
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Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(),
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MipsII::MO_NO_FLAG);
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else if (LargeGOT)
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@ -2579,7 +2576,7 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
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MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo);
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MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(),
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CallNode, RetTy);
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@ -2626,7 +2623,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
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getTargetMachine(), ArgLocs, *DAG.getContext());
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MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
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MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo);
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Function::const_arg_iterator FuncArg =
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DAG.getMachineFunction().getFunction()->arg_begin();
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bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat();
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@ -2688,7 +2685,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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(RegVT == MVT::i64 && ValVT == MVT::f64) ||
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(RegVT == MVT::f64 && ValVT == MVT::i64))
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ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
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else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
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else if (isO32() && RegVT == MVT::i32 && ValVT == MVT::f64) {
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unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
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getNextIntArgReg(ArgReg), RC);
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SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
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@ -2724,8 +2721,8 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
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unsigned Reg = MipsFI->getSRetReturnReg();
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if (!Reg) {
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Reg = MF.getRegInfo().
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createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
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Reg = MF.getRegInfo().createVirtualRegister(
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getRegClassFor(isN64() ? MVT::i64 : MVT::i32));
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MipsFI->setSRetReturnReg(Reg);
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}
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SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
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@ -2775,7 +2772,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
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*DAG.getContext());
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MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
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MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo);
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// Analyze return values.
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MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(),
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@ -2811,7 +2808,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
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if (!Reg)
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llvm_unreachable("sret virtual register not created in the entry block");
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SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
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unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
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unsigned V0 = isN64() ? Mips::V0_64 : Mips::V0;
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Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
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Flag = Chain.getValue(1);
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@ -3032,9 +3029,9 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
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return std::make_pair(0U, &Mips::CPU16RegsRegClass);
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return std::make_pair(0U, &Mips::GPR32RegClass);
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}
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if (VT == MVT::i64 && !HasMips64)
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if (VT == MVT::i64 && !hasMips64())
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return std::make_pair(0U, &Mips::GPR32RegClass);
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if (VT == MVT::i64 && HasMips64)
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if (VT == MVT::i64 && hasMips64())
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return std::make_pair(0U, &Mips::GPR64RegClass);
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// This will generate an error message
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return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
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@ -3221,7 +3218,7 @@ bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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}
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unsigned MipsTargetLowering::getJumpTableEncoding() const {
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if (IsN64)
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if (isN64())
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return MachineJumpTableInfo::EK_GPRel64BlockAddress;
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return TargetLowering::getJumpTableEncoding();
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@ -432,9 +432,10 @@ namespace llvm {
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// Subtarget Info
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const MipsSubtarget *Subtarget;
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bool HasMips64, IsN64, IsO32;
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bool hasMips64() const { return Subtarget->hasMips64(); }
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bool isO32() const { return Subtarget->isABI_O32(); }
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bool isN32() const { return Subtarget->isABI_N32(); }
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bool isN64() const { return Subtarget->isABI_N64(); }
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private:
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// Create a TargetGlobalAddress node.
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@ -38,7 +38,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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// Set up the register classes
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addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
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if (HasMips64)
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if (hasMips64())
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addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
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if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
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@ -119,10 +119,10 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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if (Subtarget->hasCnMips())
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setOperationAction(ISD::MUL, MVT::i64, Legal);
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else if (HasMips64)
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else if (hasMips64())
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setOperationAction(ISD::MUL, MVT::i64, Custom);
|
||||
|
||||
if (HasMips64) {
|
||||
if (hasMips64()) {
|
||||
setOperationAction(ISD::MULHS, MVT::i64, Custom);
|
||||
setOperationAction(ISD::MULHU, MVT::i64, Custom);
|
||||
}
|
||||
@ -1626,7 +1626,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
case Intrinsic::mips_copy_s_w:
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
|
||||
case Intrinsic::mips_copy_s_d:
|
||||
if (HasMips64)
|
||||
if (hasMips64())
|
||||
// Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
|
||||
else {
|
||||
@ -1641,7 +1641,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
||||
case Intrinsic::mips_copy_u_w:
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
|
||||
case Intrinsic::mips_copy_u_d:
|
||||
if (HasMips64)
|
||||
if (hasMips64())
|
||||
// Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
|
||||
else {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user